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? 1998 microchip technology inc. ds30605a-page 1 m microcontroller core features: high-performance risc cpu only 35 single word instructions to learn all single cycle instructions except for program branches which are two cycle operating speed: dc - 20 mhz clock input dc - 200 ns instruction cycle 4k x 14 words of program memory, 192 x 8 bytes of data memory (ram) interrupt capability (up to 12 internal/external interrupt sources) eight level deep hardware stack direct, indirect, and relative addressing modes power-on reset (por) power-up timer (pwrt) and oscillator start-up timer (ost) watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation programmable code-protection power saving sleep mode selectable oscillator options low-power, high-speed cmos eprom technology fully static design in-circuit serial programming (icsp) wide operating voltage range: 2.5v to 5.5v high sink/source current 25/25 ma commercial, industrial and extended temperature ranges low-power consumption: - < 2 ma @ 5v, 4 mhz - 22.5 m a typical @ 3v, 32 khz - < 1 m a typical standby current pin diagram peripheral features: timer0: 8-bit timer/counter with 8-bit prescaler timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler two capture, compare, pwm modules capture is 16-bit, max. resolution is 12.5 ns, compare is 16-bit, max. resolution is 200 ns, pwm maximum resolution is 10-bit 8-bit multi-channel analog-to-digital converter synchronous serial port (ssp) with enhanced spi ? and i 2 c ? universal synchronous asynchronous receiver transmitter (usart/sci) parallel slave port (psp) 8-bits wide, with external rd , wr and cs controls brown-out detection circuitry for brown-out reset (bor) device pins a/d psp pic16c63a 28 no no pic16c73b 28 yes no pic16c65b 40 no yes pic16c74b 40 yes yes pdip, windowed cerdip rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 mclr /v pp ra0/an0 ra1/an1 ra2/an2 ra3/an3/v ref ra4/t0cki ra5/ss /an4 re0/rd /an5 re1/wr /an6 re2/cs /an7 v dd v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rd0/psp0 rd1/psp1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pic16c74b pic16c63a/65b/73b/74b 28/40-pin 8-bit cmos microcontrollers
pic16c63a/65b/73b/74b ds30605a-page 2 ? 1998 microchip technology inc. pin diagrams pic16c73b mclr /v pp ra0/an0 ra1/an1 ra2/an2 ra3/an3/v ref ra4/t0cki ra5/ss /an4 v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda ?1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 sdip, soic, ssop, windowed cerdip pdip, windowed cerdip rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 mclr /v pp ra0 ra1 ra2 ra3 ra4/t0cki ra5/ss re0/rd re1/wr re2/cs v dd v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rd0/psp0 rd1/psp1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pic16c65b pic16c63a mclr /v pp ra0 ra1 ra2 ra3 ra4/t0cki ra5/ss v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda ?1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 sdip, soic, ssop, windowed cerdip rb3 rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7/rx/dt ra4/t0cki ra5/ss re0/rd re1/wr re2/cs v dd v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki nc ra3 ra2 ra1 ra0 mclr /v pp nc rb7 rb6 rb5 rb4 nc 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 6 5 4 3 2 1 44 43 42 41 40 28 27 26 25 24 23 22 21 20 19 18 nc rc0/t1oso/t1cki osc2/clkout osc1/clkin v ss v dd re2/cs re1/wr re0/rd ra5/ss ra4/t0cki rc7/rx/dt rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 v ss v dd rb0/int rb1 rb2 rb3 rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1osi/ccp2 nc 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 ra3 ra2 ra1 ra0 mclr /v pp rb7 rb6 rb5 rb4 nc nc 44 43 42 41 40 39 38 37 36 35 34 22 21 20 19 18 17 16 15 14 13 12 mqfp plcc pic16c65b pic16c65b tqfp rc1/t1osi/ccp2
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 3 pin diagrams (cont.d) rb3 rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7/rx/dt ra4/t0cki ra5/ss /an4 re0/rd /an5 re1/wr /an6 re2/cs /an7 v dd v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki nc ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 mclr /v pp nc rb7 rb6 rb5 rb4 nc 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 6 5 4 3 2 1 44 43 42 41 40 28 27 26 25 24 23 22 21 20 19 18 nc rc0/t1oso/t1cki osc2/clkout osc1/clkin v ss v dd re2/cs /an7 re1/wr /an6 re0/rd /an5 ra5/ss /an4 ra4/t0cki rc7/rx/dt rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 v ss v dd rb0/int rb1 rb2 rb3 rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1osi/ccp2 nc 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 mclr /v pp rb7 rb6 rb5 rb4 nc nc 44 43 42 41 40 39 38 37 36 35 34 22 21 20 19 18 17 16 15 14 13 12 mqfp plcc pic16c74b pic16c74b tqfp rc1/t1osi/ccp2 key features picmicro ? mid-range reference manual (ds33023) pic16c63a pic16c65b pic16c73b pic16c74b operating frequency dc - 20 mhz dc - 20 mhz dc - 20 mhz dc - 20 mhz resets (and delays) por, bor (pwrt, ost) por, bor (pwrt, ost) por, bor (pwrt, ost) por, bor (pwrt, ost) program memory (14-bit words) 4k 4k 4k 4k data memory (bytes) 192 192 192 192 interrupts 10 11 11 12 i/o ports ports a,b,c ports a,b,c,d,e ports a,b,c ports a,b,c,d,e timers 3333 capture/compare/pwm modules 2222 serial communications ssp, usart ssp, usart ssp, usart ssp, usart parallel communications psp psp 8-bit analog-to-digital module 5 input channels 8 input channels instruction set 35 instructions 35 instructions 35 instructions 35 instructions
pic16c63a/65b/73b/74b ds30605a-page 4 ? 1998 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ............................................................. 5 2.0 memory organization......................................................................................................... ........................................................ 11 3.0 i/o ports ................................................................................................................... .................................................................. 25 4.0 timer0 module ............................................................................................................... ............................................................ 37 5.0 timer1 module ............................................................................................................... ............................................................ 39 6.0 timer2 module ............................................................................................................... ............................................................ 43 7.0 capture/compare/pwm (ccp) module(s)......................................................................................... ........................................ 45 8.0 synchronous serial port (ssp) module ........................................................................................ ............................................. 51 9.0 universal synchronous asynchronous receiver transmitter (usart) ............................................................. ....................... 61 10.0 analog-to-digital converter (a/d) module................................................................................... ............................................... 75 11.0 special features of the cpu................................................................................................ ...................................................... 81 12.0 instruction set summary.................................................................................................... ........................................................ 95 13.0 development support ........................................................................................................ ........................................................ 97 14.0 electrical characteristics................................................................................................. ......................................................... 101 15.0 dc and ac characteristics graphs and tables................................................................................ ....................................... 123 16.0 packaging information ...................................................................................................... ....................................................... 125 appendix a: revision history .................................................................................................... ....................................................... 137 appendix b: device differences .................................................................................................. ..................................................... 137 appendix c: conversion considerations ........................................................................................... ............................................... 137 appendix d: migration from baseline to midrange devices......................................................................... ..................................... 138 appendix e: bit/register cross-reference list ................................................................................... ............................................. 139 index .......................................................................................................................... ........................................................................ 141 on-line support................................................................................................................ ................................................................. 147 reader response ................................................................................................................ .............................................................. 148 pic16c63a/65b/73b/74b product identification system ............................................................................ ...................................... 149 to our valued customers most current data sheet to obtain the most up-to-date version of this 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pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 5 1.0 device overview this document contains device-speci? information. additional information may be found in the picmicro ? mid-range reference manual (ds33023) which may be obtained from your local microchip sales represen- tative or downloaded from the microchip web site. the reference manual should be considered a comple- mentary document to this data sheet, and is highly rec- ommended reading for a better understanding of the device architecture and operation of the peripheral modules. there are four devices (pic16c63a, pic16c65b, pic16c73b, pic16c74b) covered by this data sheet. these devices come in 28- and 40-pin packages. the 28-pin devices do not have a parallel slave port imple- mented. the pic16c6x devices do not have the a/d module implemented. the following two ?ures are device block diagrams sorted by pin number; 28-pin for figure 1-1 and 40-pin for figure 1-2. the 28-pin and 40-pin pinouts are listed in table 1-1 and table 1-2 respectively. figure 1-1: pic16c63a/pic16c73b block diagram eprom program memory 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout mclr v dd , v ss usart porta portb portc rb0/int rb7:rb1 rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt 8 8 brown-out reset note 1: higher order bits are from the status register. 2: the a/d module is not available on the pic16c63a. ccp1 ccp2 synchronous a/d (2) timer0 timer1 timer2 serial port ra4/t0cki ra5/ss /an4 (2) ra3/an3/v ref (2) ra2/an2 (2) ra1/an1 (2) ra0/an0 (2) 8 3 4k x 14 192 x 8
pic16c63a/65b/73b/74b ds30605a-page 6 ? 1998 microchip technology inc. figure 1-2: pic16c65b/pic16c74b block diagram eprom program memory 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout mclr v dd , v ss porta portb portc portd porte ra4/t0cki ra5/ss /an4 (2) rb0/int rb7:rb1 rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt rd7/psp7:rd0/psp0 re0/rd /an5 (2) re1/wr /an6 (2) re2/cs /an7 (2) 8 8 brown-out reset note 1: higher order bits are from the status register. 2: the a/d module is not available on the pic16c65b. usart ccp1 ccp2 synchronous a/d (2) timer0 timer1 timer2 serial port ra3/an3/v ref (2) ra2/an2 (2) ra1/an1 (2) ra0/an0 (2) parallel slave port 8 3 4k x 14 192 x 8
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 7 table 1-1: pic16c63a/pic16c73b pinout description pin name dip pin# soic pin# i/o/p type buffer type description osc1/clkin 9 9 i st/cmos (3) oscillator crystal input/external clock source input. osc2/clkout 10 10 o oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, the osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. mclr /v pp 1 1 i/p st master clear (reset) input or programming voltage input. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0/an0 (4) 2 2 i/o ttl ra0 can also be analog input0 ra1/an1 (4) 3 3 i/o ttl ra1 can also be analog input1 ra2/an2 (4) 4 4 i/o ttl ra2 can also be analog input2 ra3/an3/v ref (4) 5 5 i/o ttl ra3 can also be analog input3 or analog reference voltage ra4/t0cki 6 6 i/o st ra4 can also be the clock input to the timer0 module. output is open drain type. ra5/ss /an4 (4) 7 7 i/o ttl ra5 can also be analog input4 or the slave select for the synchronous serial port. portb is a bi-directional i/o port. portb can be software programmed for internal weak pull-up on all inputs. rb0/int 21 21 i/o ttl/st (1) rb0 can also be the external interrupt pin. rb1 22 22 i/o ttl rb2 23 23 i/o ttl rb3 24 24 i/o ttl rb4 25 25 i/o ttl interrupt on change pin. rb5 26 26 i/o ttl interrupt on change pin. rb6 27 27 i/o ttl/st (2) interrupt on change pin. serial programming clock. rb7 28 28 i/o ttl/st (2) interrupt on change pin. serial programming data. portc is a bi-directional i/o port. rc0/t1oso/t1cki 11 11 i/o st rc0 can also be the timer1 oscillator output or timer1 clock input. rc1/t1osi/ccp2 12 12 i/o st rc1 can also be the timer1 oscillator input or capture2 input/compare2 output/pwm2 output. rc2/ccp1 13 13 i/o st rc2 can also be the capture1 input/compare1 output/ pwm1 output. rc3/sck/scl 14 14 i/o st rc3 can also be the synchronous serial clock input/output for both spi and i 2 c modes. rc4/sdi/sda 15 15 i/o st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo 16 16 i/o st rc5 can also be the spi data out (spi mode). rc6/tx/ck 17 17 i/o st rc6 can also be the usart asynchronous transmit or synchronous clock. rc7/rx/dt 18 18 i/o st rc7 can also be the usart asynchronous receive or synchronous data. v ss 8, 19 8, 19 p ground reference for logic and i/o pins. v dd 20 20 p positive supply for logic and i/o pins. legend: i = input o = output i/o = input/output p = power ?= not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when con?ured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when con?ured in rc oscillator mode and a cmos input otherwise. 4: the a/d module is not available on the pic16c63a.
pic16c63a/65b/73b/74b ds30605a-page 8 ? 1998 microchip technology inc. table 1-2: pic16c65b/pic16c74b pinout description pin name dip pin# plcc pin# qfp pin# i/o/p type buffer type description osc1/clkin 13 14 30 i st/cmos (4) oscillator crystal input/external clock source input. osc2/clkout 14 15 31 o oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. mclr /v pp 1 2 18 i/p st master clear (reset) input or programming voltage input. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0/an0 (5) 2 3 19 i/o ttl ra0 can also be analog input0 ra1/an1 (5) 3 4 20 i/o ttl ra1 can also be analog input1 ra2/an2 (5) 4 5 21 i/o ttl ra2 can also be analog input2 ra3/an3/v ref (5) 5 6 22 i/o ttl ra3 can also be analog input3 or analog reference voltage ra4/t0cki 6 7 23 i/o st ra4 can also be the clock input to the timer0 timer/ counter. output is open drain type. ra5/ss /an4 (5) 7 8 24 i/o ttl ra5 can also be analog input4 or the slave select for the synchronous serial port. portb is a bi-directional i/o port. portb can be software programmed for internal weak pull-up on all inputs. rb0/int 33 36 8 i/o ttl/st (1) rb0 can also be the external interrupt pin. rb1 34 37 9 i/o ttl rb2 35 38 10 i/o ttl rb3 36 39 11 i/o ttl rb4 37 41 14 i/o ttl interrupt on change pin. rb5 38 42 15 i/o ttl interrupt on change pin. rb6 39 43 16 i/o ttl/st (2) interrupt on change pin. serial programming clock. rb7 40 44 17 i/o ttl/st (2) interrupt on change pin. serial programming data. legend: i = input o = output i/o = input/output p = power ?= not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when con?ured as an external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when con?ured as general purpose i/o and a ttl input when used in the parallel slave port mode (for interfacing to a microprocessor bus). 4: this buffer is a schmitt trigger input when con?ured in rc oscillator mode and a cmos input otherwise. 5: the a/d module is not available on the pic16c65b.
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 9 portc is a bi-directional i/o port. rc0/t1oso/t1cki 15 16 32 i/o st rc0 can also be the timer1 oscillator output or a timer1 clock input. rc1/t1osi/ccp2 16 18 35 i/o st rc1 can also be the timer1 oscillator input or capture2 input/compare2 output/pwm2 output. rc2/ccp1 17 19 36 i/o st rc2 can also be the capture1 input/compare1 output/ pwm1 output. rc3/sck/scl 18 20 37 i/o st rc3 can also be the synchronous serial clock input/ output for both spi and i 2 c modes. rc4/sdi/sda 23 25 42 i/o st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo 24 26 43 i/o st rc5 can also be the spi data out (spi mode). rc6/tx/ck 25 27 44 i/o st rc6 can also be the usart asynchronous transmit or synchronous clock. rc7/rx/dt 26 29 1 i/o st rc7 can also be the usart asynchronous receive or synchronous data. portd is a bi-directional i/o port or parallel slave port when interfacing to a microprocessor bus. rd0/psp0 19 21 38 i/o st/ttl (3) rd1/psp1 20 22 39 i/o st/ttl (3) rd2/psp2 21 23 40 i/o st/ttl (3) rd3/psp3 22 24 41 i/o st/ttl (3) rd4/psp4 27 30 2 i/o st/ttl (3) rd5/psp5 28 31 3 i/o st/ttl (3) rd6/psp6 29 32 4 i/o st/ttl (3) rd7/psp7 30 33 5 i/o st/ttl (3) porte is a bi-directional i/o port. re0/rd /an5 (5) 8 9 25 i/o st/ttl (3) re0 can also be read control for the parallel slave port, or analog input5. re1/wr /an6 (5) 9 10 26 i/o st/ttl (3) re1 can also be write control for the parallel slave port, or analog input6. re2/cs /an7 (5) 10 11 27 i/o st/ttl (3) re2 can also be select control for the parallel slave port, or analog input7. v ss 12,31 13,34 6,29 p ground reference for logic and i/o pins. v dd 11,32 12,35 7,28 p positive supply for logic and i/o pins. nc 1,17,28, 40 12,13, 33,34 these pins are not internally connected. these pins should be left unconnected. table 1-2: pic16c65b/pic16c74b pinout description (cont.d) pin name dip pin# plcc pin# qfp pin# i/o/p type buffer type description legend: i = input o = output i/o = input/output p = power ?= not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when con?ured as an external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when con?ured as general purpose i/o and a ttl input when used in the parallel slave port mode (for interfacing to a microprocessor bus). 4: this buffer is a schmitt trigger input when con?ured in rc oscillator mode and a cmos input otherwise. 5: the a/d module is not available on the pic16c65b.
pic16c63a/65b/73b/74b ds30605a-page 10 ? 1998 microchip technology inc. notes:
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 11 2.0 memory organization there are two memory blocks in each of these picmicro microcontrollers. each block (program memory and data memory) has its own bus so that concurrent access can occur. additional information on device memory may be found in the picmicro ? mid-range reference manual (ds33023). 2.1 pr ogram memor y or ganization the pic16c63a/65b/73b/74b microcontrollers have a 13-bit program counter capable of addressing an 8k x 14 program memory space. each device has 4k x 14 words of program memory. accessing a location above the physically implemented address will cause a wrap- around. the reset vector is at 0000h and the interrupt vector is at 0004h. figure 2-1: program memory map and stack 2.2 data memor y or ganization the data memory is partitioned into multiple banks which contain the general purpose registers and the special function registers. bits rp1 and rp0 are the bank select bits. = 00 ? bank0 = 01 ? bank1 = 10 ? bank2 (not implemented) = 11 ? bank3 (not implemented) each bank extends up to 7fh (128 bytes). the lower locations of each bank are reserved for the special function registers. above the special function regis- ters are general purpose registers, implemented as static ram. all implemented banks contain special function registers. some ?igh use special function registers from one bank may be mirrored in another bank for code reduction and quicker access. 2.2.1 general purpose register file the register ?e can be accessed either directly, or indi- rectly through the file select register fsr (section 2.5). pc<12:0> 13 0000h 0004h 0005h 07ffh 0800h 0fffh 1000h 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program on-chip program memory (page 1) memory (page 0) call, return retfie, retlw user memory space rp1 (1) rp0 (status<6:5>) note 1: maintain this bit clear to ensure upward compati- bility with future products.
pic16c63a/65b/73b/74b ds30605a-page 12 ? 1998 microchip technology inc. figure 2-2: register file map 2.2.2 special function registers the special function registers are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. a list of these registers is give in table 2-1. the special function registers can be classi?d into two sets; core (cpu) and peripheral. those registers asso- ciated with the core functions are described in detail in this section. those related to the operation of the peripheral features are described in detail in that peripheral feature section. indf (1) tmr0 pcl status fsr porta portb portc portd (2) porte (2) pclath intcon pir1 pir2 tmr1l tmr1h t1con tmr2 t2con sspbuf sspcon ccpr1l ccpr1h ccp1con rcsta txreg rcreg ccpr2l ccpr2h ccp2con adres (3) adcon0 (3) indf (1) option_reg pcl status fsr trisa trisb trisc trisd (2) trise (2) pclath intcon pie1 pie2 pcon pr2 sspadd sspstat txsta spbrg adcon1 (3) 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h general purpose register general purpose register 7fh ffh bank 0 bank 1 file address file address unimplemented data memory locations, read as ?? note 1: not a physical register. 2: these registers are not implemented on the pic16c63a/73b, read as '0'. 3: these registers are not implemented on the pic16c63a/65b, read as '0'.
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 13 table 2-1 special function register summary addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (5) bank 0 00h indf (1) addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 01h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 02h pcl (1) program counter's (pc) least signi?ant byte 0000 0000 0000 0000 03h status (1) irp (6) rp1 (6) rp0 t o pd zdcc rr01 1xxx rr0q quuu 04h fsr (1) indirect data memory address pointer xxxx xxxx uuuu uuuu 05h porta (7) porta data latch when written: porta pins when read --0x 0000 --0u 0000 06h portb (8) portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 07h portc (8) portc data latch when written: portc pins when read xxxx xxxx uuuu uuuu 08h portd (3,8) portd data latch when written: portd pins when read xxxx xxxx uuuu uuuu 09h porte (3,8) re2 re1 re0 ---- -xxx ---- -uuu 0ah pclath (1,2) write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 0bh intcon (1) gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (3) adif (4) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 ccp2if ---- ---0 ---- ---0 0eh tmr1l holding register for the least signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 11h tmr2 timer2 modules register 0000 0000 0000 0000 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit data register 0000 0000 0000 0000 1ah rcreg usart receive data register 0000 0000 0000 0000 1bh ccpr2l capture/compare/pwm register2 (lsb) xxxx xxxx uuuu uuuu 1ch ccpr2h capture/compare/pwm register2 (msb) xxxx xxxx uuuu uuuu 1dh ccp2con ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 1eh adres (4) a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 (4) adcs1 adcs0 chs2 chs1 chs0 go/done adon 0000 00-0 0000 00-0 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', shaded locations are unimplemented, read as '0'. note 1: these registers can be addressed from either bank. 2: the upper byte of the program counter is not directly accessible. pclath is a holding register for pc<12:8> whose contents are transferred to the upper byte of the program counter. 3: portd and porte are not implemented on the pic16c63a/73b, maintain as ?? 4: a/d not implemented on the pic16c63a/65b, maintain as ?? 5: other (non power-up) resets include: external reset through mclr and the watchdog timer reset. 6: the irp and rp1 bits are reserved. always maintain these bits clear. 7: on any device reset, these pins are con?ured as inputs. 8: this is the value that will be in the port output latch.
pic16c63a/65b/73b/74b ds30605a-page 14 ? 1998 microchip technology inc. bank 1 80h indf (1) addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h pcl (1) program counter's (pc) least signi?ant byte 0000 0000 0000 0000 83h status (1) irp (6) rp1 (6) rp0 t o pd zdcc rr01 1xxx rr0q quuu 84h fsr (1) indirect data memory address pointer xxxx xxxx uuuu uuuu 85h trisa porta data direction register --11 1111 --11 1111 86h trisb portb data direction register 1111 1111 1111 1111 87h trisc portc data direction register 1111 1111 1111 1111 88h trisd (3) portd data direction register 1111 1111 1111 1111 89h trise (3) ibf obf ibov pspmode porte data direction bits 0000 -111 0000 -111 8ah pclath (1,2) write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 8bh intcon (1) gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 8ch pie1 pspie (3) adie (4) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 ccp2ie ---- ---0 ---- ---0 8eh pcon por bor ---- --qq ---- --uu 8fh unimplemented 90h unimplemented 91h unimplemented 92h pr2 timer2 period register 1111 1111 1111 1111 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 94h sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 95h unimplemented 96h unimplemented 97h unimplemented 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 9ah unimplemented 9bh unimplemented 9ch unimplemented 9dh unimplemented 9eh unimplemented 9fh adcon1 (4) pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', shaded locations are unimplemented, read as '0'. note 1: these registers can be addressed from either bank. 2: the upper byte of the program counter is not directly accessible. pclath is a holding register for pc<12:8> whose contents are transferred to the upper byte of the program counter. 3: portd and porte are not implemented on the pic16c63a/73b, maintain as ?? 4: a/d not implemented on the pic16c63a/65b, maintain as ?? 5: other (non power-up) resets include: external reset through mclr and the watchdog timer reset. 6: the irp and rp1 bits are reserved. always maintain these bits clear. 7: on any device reset, these pins are con?ured as inputs. 8: this is the value that will be in the port output latch. table 2-1 special function register summary (cont.d) addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (5)
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 15 2.2.2.1 status register the status register, shown in figure 2-3, contains the arithmetic status of the alu, the reset status and the bank select bits for data memory. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the t o and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper-three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register because these instructions do not affect the z, c or dc bits from the status register. for other instructions, not affecting any status bits, see the "instruction set summary." figure 2-3: status register (address 03h, 83h) note 1: these devices do not use bits irp and rp1 (status<7:6>). maintain these bits clear to ensure upward compatibility with future products. note 2: the c and dc bits operate as a borro w and digit borro w bit, respectively, in sub- traction. see the sublw and subwf instructions for examples. r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 t o pd z dc c r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: irp : register bank select bit (used for indirect addressing) 1 = bank 2, 3 (100h - 1ffh) - not implemented, maintain clear 0 = bank 0, 1 (00h - ffh) - not implemented, maintain clear bit 6-5: rp1:rp0 : register bank select bits (used for direct addressing) 11 = bank 3 (180h - 1ffh) - not implemented, maintain clear 10 = bank 2 (100h - 17fh) - not implemented, maintain clear 01 = bank 1 (80h - ffh) 00 = bank 0 (00h - 7fh) each bank is 128 bytes bit 4: t o : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3: pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2: z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1: dc : digit carry/borro w bit ( addwf , addlw,sublw,subwf instructions) (for borro w the polarity is reversed) 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0: c : carry/borro w bit ( addwf , addlw,sublw,subwf instructions) 1 = a carry-out from the most signi?ant bit of the result occurred 0 = no carry-out from the most signi?ant bit of the result occurred note: for borro w the polarity is reversed. a subtraction is executed by adding the twos complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high or low order bit of the source register.
pic16c63a/65b/73b/74b ds30605a-page 16 ? 1998 microchip technology inc. 2.2.2.2 option_reg register the option_reg register is a readable and writable register which contains various control bits to con?ure the tmr0 prescaler/wdt postscaler (single assign- able register known also as the prescaler), the external int interrupt, tmr0, and the weak pull-ups on portb. figure 2-4: option_reg register (address 81h) note: to achieve a 1:1 prescaler assignment for the tmr0 register, assign the prescaler to the watchdog timer. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: rbpu : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6: intedg : interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5: t0cs : tmr0 clock source select bit 1 = transition on ra4/t0cki pin 0 = internal instruction cycle clock (clkout) bit 4: t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on ra4/t0cki pin 0 = increment on low-to-high transition on ra4/t0cki pin bit 3: psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0: ps2:ps0 : prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 17 2.2.2.3 intcon register the intcon register is a readable and writable regis- ter which contains various enable and ?g bits for the tmr0 register over?w, rb port change and external rb0/int pin interrupts. figure 2-5: intcon register (address 0bh, 8bh) note: interrupt ?g bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt ?g bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peie t0ie inte rbie t0if intf rbif r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: gie: global interrupt enable bit 1 = enables all un-masked interrupts 0 = disables all interrupts bit 6: peie : peripheral interrupt enable bit 1 = enables all un-masked peripheral interrupts 0 = disables all peripheral interrupts bit 5: t0ie : tmr0 over?w interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4: iinte : rb0/int external interrupt enable bit 1 = enables the rb0/int external interrupt 0 = disables the rb0/int external interrupt bit 3: rbie : rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2: t0if : tmr0 over?w interrupt flag bit 1 = tmr0 register has over?wed (must be cleared in software) 0 = tmr0 register did not over?w bit 1: intf : rb0/int external interrupt flag bit 1 = the rb0/int external interrupt occurred (must be cleared in software) 0 = the rb0/int external interrupt did not occur bit 0: rbif : rb port change interrupt flag bit 1 = at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state
pic16c63a/65b/73b/74b ds30605a-page 18 ? 1998 microchip technology inc. 2.2.2.4 pie1 register this register contains the individual enable bits for the peripheral interrupts. figure 2-6: pie1 register (address 8ch) note: bit peie (intcon<6>) must be set to enable any peripheral interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pspie (1) adie (2) rcie txie sspie ccp1ie tmr2ie tmr1ie r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: pspie (1) : parallel slave port read/write interrupt enable bit 1 = enables the psp read/write interrupt 0 = disables the psp read/write interrupt bit 6: adie (2) : a/d converter interrupt enable bit 1 = enables the a/d interrupt 0 = disables the a/d interrupt bit 5: rcie : usart receive interrupt enable bit 1 = enables the usart receive interrupt 0 = disables the usart receive interrupt bit 4: txie : usart transmit interrupt enable bit 1 = enables the usart transmit interrupt 0 = disables the usart transmit interrupt bit 3: sspie : synchronous serial port interrupt enable bit 1 = enables the ssp interrupt 0 = disables the ssp interrupt bit 2: ccp1ie : ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1: tmr2ie : tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0: tmr1ie : tmr1 over?w interrupt enable bit 1 = enables the tmr1 over?w interrupt 0 = disables the tmr1 over?w interrupt note 1: pic16c63a/73b devices do not have a parallel slave port implemented. this bit location is reserved on these devices. always maintain this bit clear. 2: pic16c63a/65b devices do not have an a/d module. this bit location is reserved on these devices. always maintain this bit clear.
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 19 2.2.2.5 pir1 register this register contains the individual ?g bits for the peripheral interrupts. figure 2-7: pir1 register (address 0ch) note: interrupt ?g bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt ?g bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 pspif (1) adif (2) rcif txif sspif ccp1if tmr2if tmr1if r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: pspif (1) : parallel slave port read/write interrupt flag bit 1 = a read or a write operation has taken place (must be cleared in software) 0 = no read or write has occurred bit 6: adif (2) : a/d converter interrupt flag bit 1 = an a/d conversion completed (must be cleared in software) 0 = the a/d conversion is not complete bit 5: rcif : usart receive interrupt flag bit 1 = the usart receive buffer is full (cleared by reading rcreg) 0 = the usart receive buffer is empty bit 4: txif : usart transmit interrupt flag bit 1 = the usart transmit buffer is empty (cleared by writing to txreg) 0 = the usart transmit buffer is full bit 3: sspif : synchronous serial port interrupt flag bit 1 = the transmission/reception is complete (must be cleared in software) 0 = waiting to transmit/receive bit 2: ccp1if : ccp1 interrupt flag bit capture mode 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode unused in this mode bit 1: tmr2if : tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0: tmr1if : tmr1 over?w interrupt flag bit 1 = tmr1 register over?wed (must be cleared in software) 0 = tmr1 register did not over?w note 1: pic16c63a/73b devices do not have a parallel slave port implemented. this bit location is reserved on these devices. always maintain this bit clear. 2: pic16c63a/65b devices do not have an a/d module. this bit location is reserved on these devices. always maintain this bit clear.
pic16c63a/65b/73b/74b ds30605a-page 20 ? 1998 microchip technology inc. 2.2.2.6 pie2 register this register contains the individual enable bit for the ccp2 peripheral interrupt. figure 2-8: pie2 register (address 8dh) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ccp2ie r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-1: unimplemented: read as '0' bit 0: ccp2ie : ccp2 interrupt enable bit 1 = enables the ccp2 interrupt 0 = disables the ccp2 interrupt
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 21 2.2.2.7 pir2 register this register contains the ccp2 interrupt ?g bit. . figure 2-9: pir2 register (address 0dh) note: interrupt ?g bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt ?g bits are clear prior to enabling an interrupt. u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ccp2if r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-1: unimplemented: read as '0' bit 0: ccp2if : ccp2 interrupt flag bit capture mode 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode unused
pic16c63a/65b/73b/74b ds30605a-page 22 ? 1998 microchip technology inc. 2.2.2.8 pcon register the power control (pcon) register contains a ?g bit to allow differentiation between a power-on reset (por) to an external mclr reset or wdt reset. those devices with brown-out detection circuitry con- tain an additional bit to differentiate a brown-out reset condition from a power-on reset condition. figure 2-10: pcon register (address 8eh) note: if the boden con?uration bit is set, bor is ? on power-on reset. if the boden con?uration bit is clear, bor is unknown on power-on reset. the bor status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (the boden con?ura- tion bit is clear). bor must then be set by the user and checked on subsequent resets to see if it is clear, indicating a brown-out has occurred. u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-q por bor r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-2: unimplemented: read as '0' bit 1: por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0: bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs)
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 23 2.3 pcl and pcla th the program counter (pc) speci?s the address of the instruction to fetch for execution. the pc is 13 bits wide. the low byte is called the pcl register. this reg- ister is readable and writable. the high byte is called the pch register. this register contains the pc<12:8> bits and is not directly readable or writable. all updates to the pch register go through the pclath register. 2.3.1 stack the stack allows a combination of up to 8 program calls and interrupts to occur. the stack contains the return address from this branch in program execution. mid-range devices have an 8 level deep x 13-bit wide hardware stack. the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed or an interrupt causes a branch. the stack is poped in the event of a return, retlw or a retfie instruction execution. pclath is not modi?d when the stack is pushed or poped. after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the ?st push. the tenth push overwrites the second push (and so on). 2.4 pr ogram memor y p a ging the call and goto instructions provide 11 bits of address to allow branching within any 2k program memory page. when doing a call or goto instruction the upper bit of the address is provided by pclath<3>. when doing a call or goto instruction, the user must ensure that the page select bit is pro- grammed so that the desired program memory page is addressed. if a return from a call instruction (or inter- rupt) is executed, the entire 13-bit pc is pushed onto the stack. therefore, manipulation of the pclath<3> bit is not required for the return instructions (which pops the address from the stack).
pic16c63a/65b/73b/74b ds30605a-page 24 ? 1998 microchip technology inc. 2.5 indirect ad dressing, indf and fsr register s the indf register is not a physical register. address- ing indf actually addresses the register whose address is contained in the fsr register (fsr is a pointer ). this is indirect addressing. example 2-1: indirect addressing register ?e 05 contains the value 10h register ?e 06 contains the value 0ah load the value 05 into the fsr register a read of the indf register will return the value of 10h increment the value of the fsr register by one (fsr = 06) a read of the indr register now will return the value of 0ah. reading indf itself indirectly (fsr = 0) will produce 00h. writing to the indf register indirectly results in a no-operation (although status bits may be affected). a simple program to clear ram locations 20h-2fh using indirect addressing is shown in example 2-2. example 2-2: how to clear ram using indirect addressing movlw 0x20 ;initialize pointer movwf fsr ; to ram next clrf indf ;clear indf register incf fsr ;inc pointer btfss fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit (status<7>), as shown in figure 2-11. however, irp is not used in the pic16c63a/65b/73b/74b. figure 2-11: direct/indirect addressing note 1: for register ?e map detail see figure 2-2. 2: maintain rp1 and irp as clear for upward compatibility with future products. 3: not implemented. data memory (1) indirect addressing direct addressing bank select location select rp1:rp0 6 0 from opcode irp fsr register 7 0 bank select location select 00 01 10 11 bank 0 bank 1 bank 2 bank 3 not used ffh 80h 7fh 00h 17fh 100h 1ffh 180h (2) (2) (3) (3)
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 25 3.0 i/o ports some pins for these i/o ports are multiplexed with an alternate function for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. additional information on i/o ports may be found in the picmicro ? mid-range reference manual, (ds33023). 3.1 por t a and the trisa register porta is a 6-bit wide bi-directional port. the corre- sponding data direction register is trisa. setting a trisa bit (=1) will make the corresponding porta pin an input, i.e., put the corresponding output driver in a hi-impedance mode. clearing a trisa bit (=0) will make the corresponding porta pin an output, i.e., put the contents of the output latch on the selected pin. reading the porta register reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read. this value is modi?d and then written to the port data latch. pin ra4 is multiplexed with the timer0 module clock input to become the ra4/t0cki pin. the ra4/t0cki pin is a schmitt trigger input and an open drain output. all other ra port pins have ttl input levels and full cmos output drivers. on pic16c73b/74b devices, other porta pins are multiplexed with analog inputs and analog v ref input. the operation of each pin is selected by clearing/set- ting the control bits in the adcon1 register (a/d con- trol register1). the trisa register controls the direction of the ra pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. example 3-1: initializing porta bcf status, rp0 ; clrf porta ; initialize porta by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0xcf ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra<5:4> as outputs ; trisa<7:6> are always ; read as '0'. figure 3-1: block diagram of ra3:ra0 and ra5 pins figure 3-2: block diagram of ra4/t0cki pin note: on a power-on reset, these pins are con- ?ured as inputs and read as '0'. note: on a power-on reset, these pins are con- ?ured as analog inputs and read as '0'. data bus q d q ck q d q ck qd en p n wr port wr tris data latch tris latch rd tris rd port v ss v dd i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . analog input mode ttl input buffer to a/d converter (73b/74b only) (73b/74b only) data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer n v ss i/o pin (1) tmr0 clock input note 1: i/o pin has protection diodes to v ss only. q d q ck q d q ck en qd en
pic16c63a/65b/73b/74b ds30605a-page 26 ? 1998 microchip technology inc. table 3-1: porta functions table 3-2: summary of registers associated with porta name bit# buffer function ra0/an0 bit0 ttl input/output or analog input (1) ra1/an1 bit1 ttl input/output or analog input (1) ra2/an2 bit2 ttl input/output or analog input (1) ra3/an3/v ref bit3 ttl input/output or analog input (1) or v ref (1) ra4/t0cki bit4 st input/output or external clock input for timer0 output is open drain type ra5/ss /an4 bit5 ttl input/output or slave select input for synchronous serial port or analog input (1) legend: ttl = ttl input, st = schmitt trigger input note 1: on pic16c73b/74b devices only. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 05h porta ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 85h trisa porta data direction register --11 1111 --11 1111 9fh adcon1 (1) pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by porta. note 1: on pic16c73b/74b devices only.
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 27 3.2 por tb and the trisb register portb is an 8-bit wide bi-directional port. the corre- sponding data direction register is trisb. setting a trisb bit (=1) will make the corresponding portb pin an input, i.e., put the corresponding output driver in a hi-impedance mode. clearing a trisb bit (=0) will make the corresponding portb pin an output, i.e., put the contents of the output latch on the selected pin. example 3-1: initializing portb bcf status, rp0 ; clrf portb ; initialize portb by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0xcf ; value used to ; initialize data ; direction movwf trisb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is per- formed by clearing bit rbpu (option_reg<7>). the weak pull-up is automatically turned off when the port pin is con?ured as an output. the pull-ups are dis- abled on a power-on reset. figure 3-3: block diagram of rb3:rb0 pins four of portbs pins, rb7:rb4, have an interrupt on change feature. only pins con?ured as inputs can cause this interrupt to occur (i.e. any rb7:rb4 pin con- ?ured as an output is excluded from the interrupt on change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the ?ismatch outputs of rb7:rb4 are or?d together to generate the rb port change inter- rupt with ?g bit rbif (intcon<0>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the inter- rupt in the following manner: a) any read or write of portb. this will end the mismatch condition. b) clear ?g bit rbif. a mismatch condition will continue to set ?g bit rbif. reading portb will end the mismatch condition, and allow ?g bit rbif to be cleared. the interrupt on change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt on change feature. polling of portb is not recommended while using the interrupt on change feature. figure 3-4: block diagram of rb7:rb4 pins data latch rbpu (2) p v dd q d ck q d ck qd en data bus wr port wr tris rd tris rd port weak pull-up rd port rb0/int i/o pin (1) ttl input buffer note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>). schmitt trigger buffer tris latch data latch from other rbpu (2) p v dd i/o q d ck q d ck qd en qd en data bus wr port wr tris set rbif tris latch rd tris rd port rb7:rb4 pins weak pull-up rd port latch ttl input buffer pin (1) note 1: i/o pins have diode protection to v dd and v ss . st buffer rb7:rb6 in serial programming mode q3 q1 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>).
pic16c63a/65b/73b/74b ds30605a-page 28 ? 1998 microchip technology inc. table 3-3: portb functions table 3-4: summary of registers associated with portb name bit# buffer function rb0/int bit0 ttl/st (1) input/output pin or external interrupt input. internal software programmable weak pull-up. rb1 bit1 ttl input/output pin. internal software programmable weak pull-up. rb2 bit2 ttl input/output pin. internal software programmable weak pull-up. rb3 bit3 ttl input/output pin. internal software programmable weak pull-up. rb4 bit4 ttl input/output pin (with interrupt on change). internal software programmable weak pull-up. rb5 bit5 ttl input/output pin (with interrupt on change). internal software programmable weak pull-up. rb6 bit6 ttl/st (2) input/output pin (with interrupt on change). internal software programmable weak pull-up. serial programming clock. rb7 bit7 ttl/st (2) input/output pin (with interrupt on change). internal software programmable weak pull-up. serial programming data. legend: ttl = ttl input, st = schmitt trigger input note 1: this buffer is a schmitt trigger input when con?ured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 86h trisb portb data direction register 1111 1111 1111 1111 81h option_ reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged. shaded cells are not used by portb.
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 29 3.3 por tc and the trisc register portc is an 8-bit wide bi-directional port. the corre- sponding data direction register is trisc. setting a trisc bit (=1) will make the corresponding portc pin an input, i.e., put the corresponding output driver in a hi-impedance mode. clearing a trisc bit (=0) will make the corresponding portc pin an output, i.e., put the contents of the output latch on the selected pin. portc is multiplexed with several peripheral functions (table 3-5). portc pins have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in de?ing tris bits for each portc pin. some peripherals override the tris bit to make a pin an out- put, while other peripherals override the tris bit to make a pin an input. since the tris bit override is in effect while the peripheral is enabled, read-modify- write instructions ( bsf, bcf, xorwf ) with trisc as destination should be avoided. the user should refer to the corresponding peripheral section for the correct tris bit settings. example 3-1: initializing portc bcf status, rp0 ; select bank 0 clrf portc ; initialize portc by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0xcf ; value used to ; initialize data ; direction movwf trisc ; set rc<3:0> as inputs ; rc<5:4> as outputs ; rc<7:6> as inputs figure 3-5: portc block diagram (peripheral output override) port/peripheral select (2) data bus wr port wr tris rd data latch tris latch rd tris schmitt trigger q d q ck qd en p er ipher al data out 0 1 q d q ck p n v dd v ss port peripheral oe (3) peripheral input i/o pin (1) note 1: i/o pins have diode protection to v dd and v ss . 2: port/peripheral select signal selects between port data and peripheral output. 3: peripheral oe (output enable) is only activated if peripheral select is active.
pic16c63a/65b/73b/74b ds30605a-page 30 ? 1998 microchip technology inc. table 3-5: portc functions table 3-6: summary of registers associated with portc name bit# buffer type function rc0/t1oso/t1cki bit0 st input/output port pin or timer1 oscillator output/timer1 clock input rc1/t1osi bit1 st input/output port pin or timer1 oscillator input rc2/ccp1 bit2 st input/output port pin or capture1 input/compare1 output/pwm1 output rc3/sck/scl bit3 st rc3 can also be the synchronous serial clock for both spi and i 2 c modes. rc4/sdi/sda bit4 st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo bit5 st input/output port pin or synchronous serial port data output rc6 bit6 st input/output port pin rc7 bit7 st input/output port pin legend: st = schmitt trigger input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 07h portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu 87h trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged.
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 31 3.4 por td and trisd register s this section is applicable to the pic16c65b/pic16c74b devices only. portd is an 8-bit port with schmitt trigger input buff- ers. each pin is individually con?urable as an input or output. portd can be con?ured as an 8-bit wide micropro- cessor port (parallel slave port) by setting control bit pspmode (trise<4>). in this mode, the input buffers are ttl. figure 3-6: portd block diagram (in i/o port mode) data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . q d ck q d ck en qd en
pic16c63a/65b/73b/74b ds30605a-page 32 ? 1998 microchip technology inc. table 3-7: portd functions table 3-8: summary of registers associated with portd name bit# buffer type function rd0/psp0 bit0 st/ttl (1) input/output port pin or parallel slave port bit0 rd1/psp1 bit1 st/ttl (1) input/output port pin or parallel slave port bit1 rd2/psp2 bit2 st/ttl (1) input/output port pin or parallel slave port bit2 rd3/psp3 bit3 st/ttl (1) input/output port pin or parallel slave port bit3 rd4/psp4 bit4 st/ttl (1) input/output port pin or parallel slave port bit4 rd5/psp5 bit5 st/ttl (1) input/output port pin or parallel slave port bit5 rd6/psp6 bit6 st/ttl (1) input/output port pin or parallel slave port bit6 rd7/psp7 bit7 st/ttl (1) input/output port pin or parallel slave port bit7 legend: st = schmitt trigger input ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffer when in parallel slave port mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 08h portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx uuuu uuuu 88h trisd portd data direction register 1111 1111 1111 1111 89h trise ibf obf ibov pspmode porte data direction bits 0000 -111 0000 -111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by portd.
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 33 3.5 por te and trise register this section is applicable to the pic16c65b/pic16c74b devices only. the a/d multi- plexed functions are available on the pic16c74b only. porte has three pins re0/rd /an5, re1/wr /an6 and re2/cs /an7, which are individually con?urable as inputs or outputs. these pins have schmitt trigger input buffers. i/o porte becomes control inputs for the micropro- cessor port when bit pspmode (trise<4>) is set. in this mode, the user must make sure that the trise<2:0> bits are set (pins are con?ured as digital inputs). for the pic16c74b ensure adcon1 is con?- ured for digital i/o. in this mode, the input buffers are ttl. figure 3-8 shows the trise register, which also con- trols the parallel slave port operation. porte pins for the pic16c74b only are multiplexed with analog inputs. when selected as an analog input, these pins will read as '0's. trise controls the direction of the re pins, even when they are being used as analog inputs. the user must make sure to keep the pins con?ured as inputs when using them as analog inputs. figure 3-7: porte block diagram (in i/o port mode) figure 3-8: trise register (address 89h) note: on a power-on reset these pins are con- ?ured as analog inputs. data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer q d ck q d ck en qd en i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . r-0 r-0 r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 ibf obf ibov pspmode trise2 trise1 trise0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: ibf: input buffer full status bit 1 = a word has been received and is waiting to be read by the cpu 0 = no word has been received bit 6: obf : output buffer full status bit 1 = the output buffer still holds a previously written word 0 = the output buffer has been read bit 5: ibov : input buffer over?w detect bit (in microprocessor mode) 1 = a write occurred when a previously input word has not been read (must be cleared in software) 0 = no over?w occurred bit 4: pspmode : parallel slave port mode select bit 1 = parallel slave port mode 0 = general purpose i/o mode bit 3: unimplemented : read as '0' bit 2: trise2 : re2 direction control bit 1 = input 0 = output bit 1: trise1 : re2 direction control bit 1 = input 0 = output bit 0: trise0 : re2 direction control bit 1 = input 0 = output
pic16c63a/65b/73b/74b ds30605a-page 34 ? 1998 microchip technology inc. table 3-9: porte functions table 3-10: summary of registers associated with porte name bit# buffer type function re0/rd /an5 (2) bit0 st/ttl (1) input/output port pin or read control input in parallel slave port mode or analog input: rd 1 = not a read operation 0 = read operation. reads portd register (if chip selected) re1/wr /an6 (2) bit1 st/ttl (1) input/output port pin or write control input in parallel slave port mode or analog input: wr 1 = not a write operation 0 = write operation. writes portd register (if chip selected) re2/cs /an7 (2) bit2 st/ttl (1) input/output port pin or chip select control input in parallel slave port mode or analog input: cs 1 = device is not selected 0 = device is selected legend: st = schmitt trigger input ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffers when in parallel slave port mode. 2: a/d converter module multiplexing is implemented on the pic16c74b only. addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 09h porte re2 re1 re0 ---- -xxx ---- -uuu 89h trise ibf obf ibov pspmode porte data direction bits 0000 -111 0000 -111 9fh adcon1 (1) pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by porte. note 1: a/d converter module multiplexing is implemented on the pic16c74b only.
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 35 3.6 p arallel sla ve p or t the parallel slave port is implemented on the 40-pin devices only (pic16c65b and pic16c74b). portd operates as an 8-bit wide parallel slave port, or microprocessor port when control bit pspmode (trise<4>) is set. in slave mode it is asynchronously readable and writable by the external world through rd control input pin re0/rd and wr control input pin re1/wr . it can directly interface to an 8-bit microprocessor data bus. the external microprocessor can read or write the portd latch as an 8-bit latch. setting bit pspmode enables port pin re0/rd to be the rd input, re1/wr to be the wr input and re2/cs to be the cs (chip select) input. for this functionality, the corresponding data direction bits of the trise register (trise<2:0>) must be con?ured as inputs (set). for the pic16c74b, the a/d port con?uration bits pcfg2:pcfg0 (adcon1<2:0>) must be set, which will con?ure pins re2:re0 as digital i/o. a write to the psp occurs when both the cs and wr lines are ?st detected low. a read from the psp occurs when both the cs and rd lines are ?st detected low. figure 3-9: portd and porte block diagram (parallel slave port) figure 3-10: parallel slave port write waveforms data bus wr port rd rdx q d ck en qd en port pin one bit of portd set interrupt ?g pspif (pir1<7>) read chip select write rd cs wr note: i/o pin has protection diodes to v dd and v ss . ttl ttl ttl ttl q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr rd ibf obf pspif portd<7:0>
pic16c63a/65b/73b/74b ds30605a-page 36 ? 1998 microchip technology inc. figure 3-11: parallel slave port read waveforms table 3-11: registers associated with parallel slave port add. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 08h portd port data latch when written: port pins when read xxxx xxxx uuuu uuuu 09h porte re2 re1 re0 ---- -xxx ---- -uuu 89h trise ibf obf ibov pspmode porte data direction bits 0000 -111 0000 -111 0ch pir1 pspif adif (1) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie adie (1) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 9fh adcon1 (1) pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the parallel slave port. note 1: on pic16c74b only. q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr ibf pspif rd obf portd<7:0>
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 37 4.0 timer0 module the timer0 module timer/counter has the following fea- tures: 8-bit timer/counter readable and writable internal or external clock select edge select for external clock 8-bit software programmable prescaler interrupt on over?w from ffh to 00h figure 4-1 is a simpli?d block diagram of the timer0 module. additional information on timer modules is available in the picmicro ? mid-range reference manual, (ds33023). 4.1 timer0 operation timer0 can operate as a timer or as a counter. timer mode is selected by clearing bit t0cs (option_reg<5>). in timer mode, the timer0 mod- ule will increment every instruction cycle (without pres- caler). if the tmr0 register is written, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting bit t0cs (option_reg<5>). in counter mode, timer0 will increment either on every rising or falling edge of pin ra4/t0cki. the incrementing edge is determined by the timer0 source edge select bit t0se (option_reg<4>). clearing bit t0se selects the ris- ing edge. restrictions on the external clock input are discussed below. when an external clock input is used for timer0, it must meet certain requirements. the requirements ensure the external clock can be synchronized with the internal phase clock (t osc ). there is a delay in the actual incre- menting of timer0 after synchronization. additional information on external clock requirements is available in the picmicro ? mid-range reference manual, (ds33023). 4.2 pre scaler an 8-bit counter is available as a prescaler for the timer0 module, or as a postscaler for the watchdog timer, respectively (figure 4-2). for simplicity, this counter is being referred to as ?rescaler throughout this data sheet. note that there is only one prescaler available, which is mutually exclusively shared between the timer0 module and the watchdog timer. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the watchdog timer and vice-versa. the prescaler is not readable or writable. the psa and ps2:ps0 bits (option_reg<3:0>) determine the prescaler assignment and prescale ratio. clearing bit psa will assign the prescaler to the timer0 module. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. setting bit psa will assign the prescaler to the watch- dog timer (wdt). when the prescaler is assigned to the wdt, prescale values of 1:1, 1:2, ..., 1:128 are selectable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g. clrf 1, movwf 1, bsf 1,x ....etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the wdt. figure 4-1: timer0 block diagram note: writing to tmr0 when the prescaler is assigned to timer0 will clear the prescaler count, but will not change the prescaler assignment. note 1: t0cs, t0se, psa, ps2:ps0 (option_reg<5:0>). 2: the prescaler is shared with watchdog timer (refer to figure 4-2 for detailed block diagram). ra4/t0cki t0se 0 1 1 0 pin t0cs f osc /4 programmable prescaler sync with internal clocks tmr0 psout (2 cycle delay) psout data bus 8 psa ps2, ps1, ps0 set interrupt ?g bit t0if on over?w 3
pic16c63a/65b/73b/74b ds30605a-page 38 ? 1998 microchip technology inc. 4.2.1 switching prescaler assignment the prescaler assignment is fully under software con- trol, i.e., it can be changed ?n the ? during program execution. 4.3 timer0 in terrupt the tmr0 interrupt is generated when the tmr0 reg- ister over?ws from ffh to 00h. this over?w sets bit t0if (intcon<2>). the interrupt can be masked by clearing bit t0ie (intcon<5>). bit t0if must be cleared in software by the timer0 module interrupt ser- vice routine before re-enabling this interrupt. the tmr0 interrupt cannot awaken the processor from sleep since the timer is shut off during sleep. figure 4-2: block diagram of the timer0/wdt prescaler table 4-1: registers associated with timer0 note: to avoid an unintended device reset, a speci? instruction sequence (shown in the picmicro ? mid-range reference manual, (ds33023). must be executed when changing the prescaler assignment from timer0 to the wdt. this sequence must be followed even if the wdt is disabled. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 01h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 0bh, 8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 85h trisa porta data direction register --11 1111 --11 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by timer0. ra4/t0cki t0se pin m u x clkout (=fosc/4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m u x m u x watchdog timer psa 0 1 0 1 wdt time-out ps2:ps0 8 note: t0cs, t0se, psa, ps2:ps0 are (option_reg<5:0>). psa wdt enable bit m u x 0 1 0 1 data bus set ?g bit t0if on over?w 8 psa t0cs
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 39 5.0 timer1 module the timer1 module timer/counter has the following fea- tures: 16-bit timer/counter (two 8-bit registers; tmr1h and tmr1l) readable and writable (both registers) internal or external clock select interrupt on over?w from ffffh to 0000h reset from ccp module trigger timer1 has a control register, shown in figure 5-1. timer1 can be enabled/disabled by setting/clearing control bit tmr1on (t1con<0>). figure 5-2 is a simpli?d block diagram of the timer1 module. additional information on timer modules is available in the picmicro ? mid-range reference manual, (ds33023). 5.1 timer1 operation timer1 can operate in one of these modes: as a timer as a synchronous counter as an asynchronous counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). in timer mode, timer1 increments every instruction cycle. in counter mode, it increments on every rising edge of the external clock input. when the timer1 oscillator is enabled (t1oscen is set), the rc1/t1osi and rc0/t1oso/t1cki pins become inputs. that is, the trisc<1:0> value is ignored. timer1 also has an internal ?eset input? this reset can be generated by the ccp module (section 7.0). figure 5-1: t1con: timer1 control register (address 10h) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-6: unimplemented: read as '0' bit 5-4: t1ckps1:t1ckps0 : timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3: t1oscen : timer1 oscillator enable control bit 1 = oscillator is enabled 0 = oscillator is shut off note: the oscillator inverter and feedback resistor are turned off to eliminate power drain bit 2: t1sync : timer1 external clock input synchronization control bit tmr1cs = 1 1 = do not synchronize external clock input 0 = synchronize external clock input tmr1cs = 0 this bit is ignored. timer1 uses the internal clock when tmr1cs = 0. bit 1: tmr1cs : timer1 clock source select bit 1 = external clock from pin rc0/t1oso/t1cki (on the rising edge) 0 = internal clock (f osc /4) bit 0: tmr1on : timer1 on bit 1 = enables timer1 0 = stops timer1
pic16c63a/65b/73b/74b ds30605a-page 40 ? 1998 microchip technology inc. figure 5-2: timer1 block diagram tmr1h tmr1l t1osc t1sync tmr1cs t1ckps1:t1ckps0 sleep input t1oscen enable oscillator (1) f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 rc0/t1oso/t1cki rc1/t1osi note 1: when the t1oscen bit is cleared, the inverter and feedback resistor are turned off. this eliminates power drain. set ?g bit tmr1if on over?w tmr1
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 41 5.2 timer1 oscillator a crystal oscillator circuit is built-in between pins t1osi (input) and t1oso (ampli?r output). it is enabled by setting control bit t1oscen (t1con<3>). the oscilla- tor is a low power oscillator rated up to 200 khz. it will continue to run during sleep. it is primarily intended for a 32 khz crystal. table 5-1 shows the capacitor selection for the timer1 oscillator. the timer1 oscillator is identical to the lp oscillator. the user must provide a software time delay to ensure proper oscillator start-up. table 5-1: capacitor selection for the timer1 oscillator 5.3 timer1 interrupt the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the tmr1 interrupt, if enabled, is generated on over?w which is latched in interrupt ?g bit tmr1if (pir1<0>). this interrupt can be enabled/disabled by setting/clear- ing tmr1 interrupt enable bit tmr1ie (pie1<0>). 5.4 resetting timer1 using a ccp t rig g er output if the ccp module is con?ured in compare mode to generate a ?pecial event trigger" (ccp1m3:ccp1m0 = 1011 ), this signal will reset timer1 and start an a/d conversion (if the a/d module is enabled). timer1 must be con?ured for either timer or synchro- nized counter mode to take advantage of this feature. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a spe- cial event trigger from ccp1, the write will take prece- dence. in this mode of operation, the ccpr1h:ccpr1l regis- ters pair effectively becomes the period register for timer1. table 5-2: registers associated with timer1 as a timer/counter osc type freq c1 c2 lp 32 khz 33 pf 33 pf 100 khz 15 pf 15 pf 200 khz 15 pf 15 pf these values are for design guidance only. crystals tested: 32.768 khz epson c-001r32.768k-a 20 ppm 100 khz epson c-2 100.00 kc-p 20 ppm 200 khz std xtl 200.000 khz 20 ppm note 1: higher capacitance increases the stability of the oscillator but also increases the start- up time. 2: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropri- ate values of external components. note: the special event triggers from the ccp1 module will not set interrupt ?g bit tmr1if (pir1<0>). address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 (1) adif (1) (1) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 (1) adie (1) (1) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 0eh tmr1l holding register for the least signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the timer1 module. note 1: these bits are reserved, maintain as '0'.
pic16c63a/65b/73b/74b ds30605a-page 42 ? 1998 microchip technology inc. notes:
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 43 6.0 timer2 module the timer2 module timer has the following features: 8-bit timer (tmr2 register) 8-bit period register (pr2) readable and writable (both registers) software programmable prescaler (1:1, 1:4, 1:16) software programmable postscaler (1:1 to 1:16) interrupt on tmr2 match of pr2 ssp module optional use of tmr2 output to gen- erate clock shift timer2 has a control register, shown in figure 6-1. timer2 can be shut off by clearing control bit tmr2on (t2con<2>) to minimize power consumption. figure 6-2 is a simpli?d block diagram of the timer2 module. additional information on timer modules is available in the picmicro ? mid-range reference manual, (ds33023). 6.1 timer2 operation timer2 can be used as the pwm time-base for pwm mode of the ccp module. the tmr2 register is readable and writable, and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits t2ckps1:t2ckps0 (t2con<1:0>). the match output of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr2 interrupt (latched in ?g bit tmr2if, (pir1<1>)). the prescaler and postscaler counters are cleared when any of the following occurs: a write to the tmr2 register a write to the t2con register any device reset (power-on reset, mclr reset, watchdog timer reset, or brown-out reset) tmr2 is not cleared when t2con is written. figure 6-1: t2con: timer2 control register (address 12h) u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: unimplemented: read as '0' bit 6-3: toutps3:toutps0 : timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 1111 = 1:16 postscale bit 2: tmr2on : timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0: t2ckps1:t2ckps0 : timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16
pic16c63a/65b/73b/74b ds30605a-page 44 ? 1998 microchip technology inc. 6.2 timer2 interrupt the timer2 module has an 8-bit period register pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is ini- tialized to ffh upon reset. 6.3 output of tmr2 the output of tmr2 (before the postscaler) is fed to the synchronous serial port module, which optionally uses it to generate shift clock. figure 6-2: timer2 block diagram table 6-1: registers associated with timer2 as a timer/counter comparator tmr2 sets ?g tmr2 reg output (1) reset postscaler prescaler pr2 reg 2 f osc /4 1:1 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if note 1: tmr2 register output can be software selected by the ssp module as a baud clock. to address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 (1) adif (1) (1) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 (1) adie (1) (1) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 11h tmr2 timer2 modules register 0000 0000 0000 0000 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 92h pr2 timer2 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the timer2 module. note 1: these bits are reserved, maintain as '0'.
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 45 7.0 capture/compare/pwm (ccp) module(s) each ccp (capture/compare/pwm) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register or as a pwm master/slave duty cycle register. table 7-1 shows the timer resources of the ccp module modes. the operation of ccp1 is identical to that of ccp2, with the exception of the special trigger. therefore, opera- tion of a ccp module in the following sections is described with respect to ccp1. table 7-2 shows the interaction of the ccp modules. ccp1 module capture/compare/pwm register1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp1con register controls the operation of ccp1. all are readable and writable. ccp2 module capture/compare/pwm register2 (ccpr2) is com- prised of two 8-bit registers: ccpr2l (low byte) and ccpr2h (high byte). the ccp2con register controls the operation of ccp2. all are readable and writable. additional information on the ccp module is available in the picmicro ? mid-range reference manual, (ds33023). table 7-1: ccp mode - timer resource table 7-2: interaction of two ccp modules figure 7-1: ccp1con register (address 17h) / ccp2con register (address 1dh) ccp mode timer resource capture compare pwm timer1 timer1 timer2 ccpx mode ccpy mode interaction capture capture same tmr1 time-base. capture compare the compare should be con?ured for the special event trigger, which clears tmr1. compare compare the compare(s) should be con?ured for the special event trigger, which clears tmr1. pwm pwm the pwms will have the same frequency, and update rate (tmr2 interrupt). pwm capture none pwm compare none u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ccpxx ccpxy ccpxm3 ccpxm2 ccpxm1 ccpxm0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7-6: unimplemented: read as '0' bit 5-4: ccpxx:ccpxy : pwm least signi?ant bits capture mode: unused compare mode: unused pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccprxl. bit 3-0: ccpxm3:ccpxm0 : ccpx mode select bits 0000 = capture/compare/pwm off (resets ccpx module) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, set output on match (ccpxif bit is set) 1001 = compare mode, clear output on match (ccpxif bit is set) 1010 = compare mode, generate software interrupt on match (ccpxif bit is set, ccpx pin is unaffected) 1011 = compare mode, trigger special event (ccpxif bit is set; ccp1 resets tmr1; ccp2 resets tmr1 and starts an a/d conversion (if a/d module is enabled)) 11xx = pwm mode
pic16c63a/65b/73b/74b ds30605a-page 46 ? 1998 microchip technology inc. 7.1 capture mode in capture mode, ccpr1h:ccpr1l captures the 16-bit value of the tmr1 register when an event occurs on pin rc2/ccp1. an event is de?ed as: every falling edge every rising edge every 4th rising edge every 16th rising edge an event is selected by control bits ccp1m3:ccp1m0 (ccp1con<3:0>). when a capture is made, the inter- rupt request ?g bit ccp1if (pir1<2>) is set. it must be cleared in software. if another capture occurs before the value in register ccpr1 is read, the old captured value will be lost. 7.1.1 ccp pin configuration in capture mode, the rc2/ccp1 pin should be con?- ured as an input by setting the trisc<2> bit. figure 7-2: capture mode operation block diagram 7.1.2 timer1 mode selection timer1 must be running in timer mode or synchronized counter mode for the ccp module to use the capture feature. in asynchronous counter mode, the capture operation may not work. 7.1.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit ccp1ie (pie1<2>) clear to avoid false interrupts and should clear the ?g bit ccp1if following any such change in operating mode. 7.1.4 ccp prescaler there are four prescaler settings, speci?d by bits ccp1m3:ccp1m0. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. this means that any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared, therefore the ?st capture may be from a non-zero prescaler. example 7-1 shows the recom- mended method for switching between capture pres- calers. this example also clears the prescaler counter and will not generate the ?alse interrupt. example 7-1: changing between capture prescalers clrf ccp1con ;turn ccp module off movlw new_capt_ps ;load the w reg with ; the new prescaler ; mode value and ccp on movwf ccp1con ;load ccp1con with this ; value note: if the rc2/ccp1 is con?ured as an out- put, a write to the port can cause a capture condition. ccpr1h ccpr1l tmr1h tmr1l set ?g bit ccp1if (pir1<2>) capture enable qs ccp1con<3:0> rc2/ccp1 prescaler ? 1, 4, 16 and edge detect pin
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 47 7.2 compare mode in compare mode, the 16-bit ccpr1 register value is constantly compared against the tmr1 register pair value. when a match occurs, the rc2/ccp1 pin is: driven high driven low remains unchanged the action on the pin is based on the value of control bits ccp1m3:ccp1m0 (ccp1con<3:0>). at the same time, interrupt ?g bit ccp1if is set. figure 7-3: compare mode operation block diagram 7.2.1 ccp pin configuration the user must con?ure the rc2/ccp1 pin as an out- put by clearing the trisc<2> bit. 7.2.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 7.2.3 software interrupt mode when generate software interrupt is chosen the ccp1 pin is not affected. only a ccp interrupt is generated (if enabled). 7.2.4 special event trigger in this mode, an internal hardware trigger is generated which may be used to initiate an action. the special event trigger output of ccp1 resets the tmr1 register pair. this allows the ccpr1 register to effectively be a 16-bit programmable period register for timer1. the special trigger output of ccp2 resets the tmr1 register pair, and starts an a/d conversion (if the a/d module is enabled). table 7-3: registers associated with capture, compare, and timer1 ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger (ccp2 only) set ?g bit ccp1if (pir1<2>) match rc2/ccp1 trisc<2> ccp1con<3:0> mode select output enable pin special event trigger will reset timer1, but not set interrupt ?g bit tmr1if (pir1<0>), and set bit go/done (adcon0<2>), which starts an a/d conversion note: clearing the ccp1con register will force the rc2/ccp1 compare output latch to the default low level. this is not the data latch. note: the special event trigger from the ccp2 module will not set interrupt ?g bit tmr1if (pir1<0>). address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 (1) adif (1) (1) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 (1) adie (1) (1) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 87h trisc portc data direction register 1111 1111 1111 1111 0eh tmr1l holding register for the least signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most signi?ant byte of the 16-bit tmr1register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by capture and timer1. note 1: these bits/registers are reserved, maintain as '0'.
pic16c63a/65b/73b/74b ds30605a-page 48 ? 1998 microchip technology inc. 7.3 pwm m ode in pulse width modulation (pwm) mode, the ccp1 pin produces up to a 10-bit resolution pwm output. since the ccp1 pin is multiplexed with the portc data latch, the trisc<2> bit must be cleared to make the ccp1 pin an output. figure 7-4 shows a simpli?d block diagram of the ccp module in pwm mode. for a step by step procedure on how to set up the ccp module for pwm operation, see section 7.3.3. figure 7-4: simplified pwm block diagram a pwm output (figure 7-5) has a time base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/ period). figure 7-5: pwm output 7.3.1 pwm period the pwm period is speci?d by writing to the pr2 reg- ister. the pwm period can be calculated using the fol- lowing formula: pwm period = [(pr2) + 1] 4 t osc (tmr2 prescale value) pwm frequency is de?ed as 1 / [pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: tmr2 is cleared the ccp1 pin is set (exception: if pwm duty cycle = 0%, the ccp1 pin will not be set) the pwm duty cycle is latched from ccpr1l into ccpr1h 7.3.2 pwm duty cycle the pwm duty cycle is speci?d by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available: the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr1l:ccp1con<5:4>. the following equation is used to calculate the pwm duty cycle in time: pwm duty cycle = (ccpr1l:ccp1con<5:4>) t osc (tmr2 prescale value ) ccpr1l and ccp1con<5:4> can be written to at any time, but the duty cycle value is not latched into ccpr1h until after a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read-only register. the ccpr1h register and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. when the ccpr1h and 2-bit latch match tmr2 con- catenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the ccp1 pin is cleared.= maximum pwm resolution (bits) for a given pwm fre- quency: for an example pwm period and duty cycle calcula- tion, see the picmicro ? mid-range reference manual (ds33023). note: clearing the ccp1con register will force the ccp1 pwm output latch to the default low level. this is not the portc i/o data latch. ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) r q s duty cycle registers ccp1con<5:4> clear timer, ccp1 pin and latch d.c. trisc<2> rc2/ccp1 note 1: 8-bit timer is concatenated with 2-bit internal q clock or 2 bits of the prescaler to create 10-bit time-base. period duty cycle tmr2 = pr2 tmr2 = duty cycle tmr2 = pr2 note: the timer2 postscaler (see section 6.0) is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different fre- quency than the pwm output. note: if the pwm duty cycle value is longer than the pwm period, the ccp1 pin will not be cleared. f osc f pwm --------------- - ? ?? log 2 () log ----------------------------- bits =
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 49 7.3.3 set-up for pwm operation the following steps should be taken when con?uring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 regis- ter. 2. set the pwm duty cycle by writing to the ccpr1l register and ccp1con<5:4> bits. 3. make the ccp1 pin an output by clearing the trisc<2> bit. 4. set the tmr2 prescale value and enable timer2 by writing to t2con. 5. con?ure the ccp1 module for pwm operation. table 7-4: example pwm frequencies and resolutions at 20 mhz table 7-5: registers associated with pwm and timer2 pwm frequency 1.22 khz 4.88 khz 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescaler (1, 4, 16) 16 4 1111 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 5.5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 (1) adif (1) (1) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 (1) adie (1) (1) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 87h trisc portc data direction register 1111 1111 1111 1111 11h tmr2 timer2 modules register 0000 0000 0000 0000 92h pr2 timer2 modules period register 1111 1111 1111 1111 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by pwm and timer2. note 1: these bits/registers are reserved, maintain as '0'.
pic16c63a/65b/73b/74b ds30605a-page 50 ? 1998 microchip technology inc. notes:
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 51 8.0 synchronous serial port (ssp) module 8.1 ssp module over vie w the synchronous serial port (ssp) module is a serial interface useful for communicating with other periph- eral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, dis- play drivers, a/d converters, etc. the ssp module can operate in one of two modes: serial peripheral interface (spi) inter-integrated circuit (i 2 c) for more information on ssp operation (including an i 2 c overview), refer to the picmicro ? mid-range ref- erence manual (ds33023). also, refer to application note an578, ?se of the ssp module in the i 2 c multi- master environment.
pic16c63a/65b/73b/74b ds30605a-page 52 ? 1998 microchip technology inc. figure 8-1: sspstat: sync serial port status register (address 94h) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a p s r/w ua bf r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7: smp: spi data input sample phase spi master oper ation 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi sla v e mode smp must be cleared when spi is used in slave mode bit 6: cke : spi clock edge select ckp = 0 1 = data transmitted on rising edge of sck 0 = data transmitted on falling edge of sck ckp = 1 1 = data transmitted on falling edge of sck 0 = data transmitted on rising edge of sck bit 5: d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4: p : stop bit (i 2 c mode only. this bit is cleared when the ssp module is disabled, or when the start bit is detected last, sspen is cleared) 1 = indicates that a stop bit has been detected last (this bit is '0' on reset) 0 = stop bit was not detected last bit 3: s : start bit (i 2 c mode only. this bit is cleared when the ssp module is disabled, or when the stop bit is detected last, sspen is cleared) 1 = indicates that a start bit has been detected last (this bit is '0' on reset) 0 = start bit was not detected last bit 2: r/w : read/write bit information (i 2 c mode only) this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit, or a ck bit. 1 = read 0 = write bit 1: ua : update address (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0: bf : buffer full status bit receiv e (spi and i 2 c modes) 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty t r ansmit (i 2 c mode only) 1 = transmit in progress, sspbuf is full 0 = transmit complete, sspbuf is empty
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 53 figure 8-2: sspcon: sync serial port control register (address 14h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7: wcol : write collision detect bit 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6: sspov : receive over?w indicator bit in spi mode 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of over?w, the data in sspsr is lost. over?w can only occur in slave mode. the user must read the sspbuf, even if only transmitting data, to avoid setting over?w. in master operation, the over?w bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf register. 0 = no over?w in i 2 c mode 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a "don? care" in transmit mode. sspov must be cleared in software in either mode. 0 = no over?w bit 5: sspen : synchronous serial port enable bit in spi mode 1 = enables serial port and con?ures sck, sdo, and sdi as serial port pins 0 = disables serial port and con?ures these pins as i/o port pins in i 2 c mode 1 = enables the serial port and con?ures the sda and scl pins as serial port pins 0 = disables serial port and con?ures these pins as i/o port pins in both modes, when enabled, these pins must be properly con?ured as input or output. bit 4: ckp : clock polarity select bit in spi mode 1 = idle state for clock is a high level 0 = idle state for clock is a low level in i 2 c mode sck release control 1 = enable clock 0 = holds clock low (clock stretch) (used to ensure data setup time) bit 3-0: sspm3:sspm0 : synchronous serial port mode select bits 0000 = spi master operation, clock = f osc /4 0001 = spi master operation, clock = f osc /16 0010 = spi master operation, clock = f osc /64 0011 = spi master operation, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin. ss pin control enabled. 0101 = spi slave mode, clock = sck pin. ss pin control disabled. ss can be used as i/o pin 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1011 = i 2 c firmware controlled master operation (slave idle) 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled
pic16c63a/65b/73b/74b ds30605a-page 54 ? 1998 microchip technology inc. 8.2 spi mode this section contains register de?itions and opera- tional characteristics of the spi module. additional information on spi operation may be found in the picmicro ? mid-range reference manual (ds33023). 8.2.1 operation of ssp module in spi mode a block diagram of the ssp module in spi mode is shown in figure 8-3. the spi mode allows 8-bits of data to be synchro- nously transmitted and received simultaneously. to accomplish communication, typically three pins are used: serial data out (sdo) rc5/sdo serial data in (sdi) rc4/sdi/sda serial clock (sck) rc3/sck/scl additionally a fourth pin may be used when in a slave mode of operation: slave select (ss ) ra5/ss /an4 when initializing the spi, several options need to be speci?d. this is done by programming the appropriate control bits in the sspcon register (sspcon<5:0>) and sspstat<7:6>. these control bits allow the fol- lowing to be speci?d: master operation (sck is the clock output) slave mode (sck is the clock input) clock polarity (idle state of sck) clock edge (output data on rising/falling edge of sck) clock rate (master operation only) slave select mode (slave mode only) to enable the serial port, ssp enable bit, sspen (sspcon<5>) must be set. to reset or recon?ure spi mode, clear bit sspen, re-initialize the sspcon reg- ister and then set bit sspen. this con?ures the sdi, sdo, sck and ss pins as serial port pins. for the pins to behave as the serial port function, they must have their data direction bits (in the trisc register) appro- priately programmed. that is: sdi must have trisc<4> set sdo must have trisc<5> cleared sck (master operation) must have trisc<3> cleared sck (slave mode) must have trisc<3> set ?s must have trisa<5> set figure 8-3: ssp block diagram (spi mode) note: when the spi is in slave mode with ss pin control enabled, (sspcon<3:0> = 0100 ) the spi module will reset if the ss pin is set to v dd . note: if the spi is used in slave mode with cke = '1', then the ss pin control must be enabled. read write internal data bus rc4/sdi/sda rc5/sdo ra5/ss /an4 rc3/sck/ sspsr reg sspbuf reg sspm3:sspm0 bit0 shift clock ss control enable edge select clock select tmr2 output t cy prescaler 4, 16, 64 trisc<3> 2 edge select 2 4 scl
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 55 table 8-1: registers associated with spi operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 (1) adif (1) (1) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 (1) adie (1) (1) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 87h trisc portc data direction register 1111 1111 1111 1111 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 85h trisa porta data direction register --11 1111 --11 1111 94h sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the ssp in spi mode. note 1: always maintain these bits clear.
pic16c63a/65b/73b/74b ds30605a-page 56 ? 1998 microchip technology inc. 8.3 ssp i 2 c operation the ssp module in i 2 c mode fully implements all slave functions, except general call support, and provides interrupts on start and stop bits in hardware to facilitate ?mware implementations of the master functions. the ssp module implements the standard mode speci?a- tions as well as 7-bit and 10-bit addressing. two pins are used for data transfer. these are the rc3/ sck/scl pin, which is the clock (scl), and the rc4/ sdi/sda pin, which is the data (sda). the user must con?ure these pins as inputs or outputs through the trisc<4:3> bits. the ssp module functions are enabled by setting ssp enable bit sspen (sspcon<5>). figure 8-4: ssp block diagram (i 2 c mode) the ssp module has ?e registers for i 2 c operation. these are the: ssp control register (sspcon) ssp status register (sspstat) serial receive/transmit buffer (sspbuf) ssp shift register (sspsr) - not directly acces- sible ssp address register (sspadd) the sspcon register allows control of the i 2 c opera- tion. four mode selection bits (sspcon<3:0>) allow one of the following i 2 c modes to be selected: ? 2 c slave mode (7-bit address) ? 2 c slave mode (10-bit address) ? 2 c slave mode (7-bit address), with start and stop bit interrupts enabled ? 2 c slave mode (10-bit address), with start and stop bit interrupts enabled ? 2 c firmware controlled master operation, slave is idle selection of any i 2 c mode, with the sspen bit set, forces the scl and sda pins to be open drain, pro- vided these pins are programmed to inputs by setting the appropriate trisc bits. additional information on ssp i 2 c operation may be found in the picmicro ? mid-range reference manual (ds33023). 8.3.1 slave mode in slave mode, the scl and sda pins must be con?- ured as inputs (trisc<4:3> set). the ssp module will override the input state with the output data when required (slave-transmitter). when an address is matched or the data transfer after an address match is received, the hardware automati- cally will generate the acknowledge (a ck ) pulse, and then load the sspbuf register with the received value currently in the sspsr register. there are certain conditions that will cause the ssp module not to give this a ck pulse. these are if either (or both): a) the buffer full bit bf (sspstat<0>) was set before the transfer was received. b) the over?w bit sspov (sspcon<6>) was set before the transfer was received. in this case, the sspsr register value is not loaded into the sspbuf, but bit sspif (pir1<3>) is set. table 8-2 shows what happens when a data transfer byte is received, given the status of bits bf and sspov. the shaded cells show the condition where user software did not properly clear the over?w condi- tion. flag bit bf is cleared by reading the sspbuf reg- ister while bit sspov is cleared through software. the scl clock input must have a minimum high and low for proper operation. the high and low times of the i 2 c speci?ation as well as the requirement of the ssp module is shown in timing parameter #100 and param- eter #101. read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) rc3/sck/scl rc4/ shift clock msb sdi/ lsb sda
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 57 8.3.1.1 addressing once the ssp module has been enabled, it waits for a start condition to occur. following the start condi- tion, the 8-bits are shifted into the sspsr register. all incoming bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is compared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match, and the bf and sspov bits are clear, the following events occur: a) the sspsr register value is loaded into the sspbuf register. b) the buffer full bit, bf is set. c) an a ck pulse is generated. d) ssp interrupt ?g bit, sspif (pir1<3>) is set (interrupt is generated if enabled) - on the falling edge of the ninth scl pulse. in 10-bit address mode, two address bytes need to be received by the slave. the ?e most signi?ant bits (msbs) of the ?st address byte specify if this is a 10-bit address. bit r/w (sspstat<2>) must specify a write so the slave device will receive the second address byte. for a 10-bit address the ?st byte would equal 1111 0 a9 a8 0 ? where a9 and a8 are the two msbs of the address. the sequence of events for 10-bit address is as follows with steps 7- 9 for slave-transmit- ter: 1. receive ?st (high) byte of address (bits sspif, bf, and bit ua (sspstat<1>) are set). 2. update the sspadd register with second (low) byte of address (clears bit ua and releases the scl line). 3. read the sspbuf register (clears bit bf) and clear ?g bit sspif. 4. receive second (low) byte of address (bits sspif, bf, and ua are set). 5. update the sspadd register with the ?st (high) byte of address. if match releases scl line, this will clear bit ua. 6. read the sspbuf register (clears bit bf) and clear ?g bit sspif. 7. receive repeated start condition. 8. receive ?st (high) byte of address (bits sspif and bf are set). 9. read the sspbuf register (clears bit bf) and clear ?g bit sspif. table 8-2: data transfer received byte actions status bits as data transfer is received sspsr ? sspbuf generate a ck pulse set bit sspif (ssp interrupt occurs if enabled) bf sspov 00 ye s ye s ye s 10 no no yes 11 no no yes 0 1 ye s no ye s note: shaded cells show the conditions where the user software did not properly clear the over?w condition.
pic16c63a/65b/73b/74b ds30605a-page 58 ? 1998 microchip technology inc. 8.3.1.2 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register. when the address byte over?w condition exists, then no acknowledge (a ck ) pulse is given. an over?w con- dition is de?ed as either bit bf (sspstat<0>) is set or bit sspov (sspcon<6>) is set. an ssp interrupt is generated for each data transfer byte. flag bit sspif (pir1<3>) must be cleared in soft- ware. the sspstat register is used to determine the status of the byte. figure 8-5: i 2 c waveforms for reception (7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 56 7 89 123 4 bus master terminates transfer bit sspov is set because the sspbuf register is still full. cleared in software sspbuf register is read a ck receiving data receiving data d0 d1 d2 d3 d4 d5 d6 d7 a ck r/w =0 receiving address sspif (pir1<3>) bf (sspstat<0>) sspov (sspcon<6>) a ck a ck is not sent.
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 59 8.3.1.3 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the a ck pulse will be sent on the ninth bit, and pin rc3/sck/scl is held low. the transmit data must be loaded into the ssp- buf register, which also loads the sspsr register. then pin rc3/sck/scl should be enabled by setting bit ckp (sspcon<4>). the master must monitor the scl pin prior to asserting another clock pulse. the slave devices may be holding off the master by stretch- ing the clock. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time (figure 8-6). an ssp interrupt is generated for each data transfer byte. flag bit sspif must be cleared in software, and the sspstat register is used to determine the status of the byte. flag bit sspif is set on the falling edge of the ninth clock pulse. as a slave-transmitter, the a ck pulse from the master- receiver is latched on the rising edge of the ninth scl input pulse. if the sda line was high (not a ck ), then the data transfer is complete. when the a ck is latched by the slave, the slave logic is reset (resets sspstat reg- ister) and the slave then monitors for another occur- rence of the start bit. if the sda line was low (a ck ), the transmit data must be loaded into the sspbuf reg- ister, which also loads the sspsr register. then pin rc3/sck/scl should be enabled by setting bit ckp. figure 8-6: i 2 c waveforms for transmission (7-bit address) sda scl sspif (pir1<3>) bf (sspstat<0>) ckp (sspcon<4>) a7 a6 a5 a4 a3 a2 a1 a ck d7 d6 d5 d4 d3 d2 d1 d0 a ck transmitting data r/w = 1 receiving address 123456789 123456789 p cleared in software sspbuf is written in software from ssp interrupt service routine set bit after writing to sspbuf s data in sampled scl held low while cpu responds to sspif (the sspbuf must be written-to before the ckp bit can be set)
pic16c63a/65b/73b/74b ds30605a-page 60 ? 1998 microchip technology inc. 8.3.2 master operation master operation is supported in ?mware using inter- rupt generation on the detection of the start and stop conditions. the stop (p) and start (s) bits are cleared from a reset or when the ssp module is disabled. the stop (p) and start (s) bits will toggle based on the start and stop conditions. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle and both the s and p bits are clear. in master operation, the scl and sda lines are manip- ulated in ?mware by clearing the corresponding trisc<4:3> bit(s). the output level is always low, irre- spective of the value(s) in portc<4:3>. so when transmitting data, a '1' data bit must have the trisc<4> bit set (input) and a '0' data bit must have the trisc<4> bit cleared (output). the same scenario is true for the scl line with the trisc<3> bit. the following events will cause ssp interrupt flag bit, sspif, to be set (ssp interrupt if enabled): start condition stop condition data transfer byte transmitted/received master operation can be done with either the slave mode idle (sspm3:sspm0 = 1011 ) or with the slave active. when both master operation and slave modes are used, the software needs to differentiate the source(s) of the interrupt. for more information on master operation, see an554 - software implementation of i 2 c bus master . 8.3.3 multi-master operation in multi-master operation, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the ssp module is disabled. the stop (p) and start (s) bits will toggle based on the start and stop conditions. control of the i 2 c bus may be taken when bit p (sspstat<4>) is set, or the bus is idle and both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be moni- tored to see if the signal level is the expected output level. this check only needs to be done when a high level is output. if a high level is expected and a low level is present, the device needs to release the sda and scl lines (set trisc<4:3>). there are two stages where this arbitration can be lost, these are: address transfer data transfer when the slave logic is enabled, the slave continues to receive. if arbitration was lost during the address trans- fer stage, communication to the device may be in progress. if addressed, an a ck pulse will be gener- ated. if arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time. for more information on master operation, see an578 - use of the ssp module in the of i 2 c multi-master environment . table 8-3: registers associated with i 2 c operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh, 8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 (1) adif (1) (1) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 (1) adie (1) (1) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 94h sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 87h trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by ssp module in spi mode. note 1: these bits are unimplemented, read as '0'.
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 61 9.0 universal synchronous asynchronous receiver transmitter (usart) the universal synchronous asynchronous receiver transmitter (usart) module is one of the two serial i/o modules. (usart is also known as a serial com- munications interface or sci). the usart can be con- ?ured as a full duplex asynchronous system that can communicate with peripheral devices such as crt ter- minals and personal computers, or it can be con?ured as a half duplex synchronous system that can commu- nicate with peripheral devices such as a/d or d/a inte- grated circuits, serial eeproms etc. the usart can be con?ured in the following modes: asynchronous (full duplex) synchronous - master (half duplex) synchronous - slave (half duplex) bit spen (rcsta<7>), and bits trisc<7:6>, have to be set in order to con?ure pins rc6/tx/ck and rc7/ rx/dt as the universal synchronous asynchronous receiver transmitter. figure 9-1: txsta: transmit status and control register (address 98h) r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r-1 r/w-0 csrc tx9 txen sync brgh trmt tx9d r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7: csrc : clock source select bit asynchronous mode don? care synchronous mode 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6: tx9 : 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5: txen : transmit enable bit 1 = transmit enabled 0 = transmit disabled note: sren/cren overrides txen in sync mode. bit 4: sync : usart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3: unimplemented: read as '0' bit 2: brgh : high baud rate select bit asynchronous mode 1 = high speed 0 = low speed synchronous mode unused in this mode bit 1: trmt : transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0: tx9d : 9th bit of transmit data. can be parity bit.
pic16c63a/65b/73b/74b ds30605a-page 62 ? 1998 microchip technology inc. figure 9-2: rcsta: receive status and control register (address 18h) r/w-0 r/w-0 r/w-0 r/w-0 u-0 r-0 r-0 r-x spen rx9 sren cren ferr oerr rx9d r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7: spen : serial port enable bit 1 = serial port enabled (con?ures rc7/rx/dt and rc6/tx/ck pins as serial port pins) 0 = serial port disabled bit 6: rx9 : 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5: sren : single receive enable bit asynchronous mode don? care synchronous mode - master 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode - sla v e unused in this mode bit 4: cren : continuous receive enable bit asynchronous mode 1 = enables continuous receive 0 = disables continuous receive synchronous mode 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3: unimplemented: read as '0' bit 2: ferr : framing error bit 1 = framing error (can be updated by reading rcreg register and receive next valid byte) 0 = no framing error bit 1: oerr : overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0: rx9d : 9th bit of received data (can be parity bit)
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 63 9.1 usar t baud rate generator (brg) the brg supports both the asynchronous and syn- chronous modes of the usart. it is a dedicated 8-bit baud rate generator. the spbrg register controls the period of a free running 8-bit timer. in asynchronous mode bit brgh (txsta<2>) also controls the baud rate. in synchronous mode bit brgh is ignored. table 9-1 shows the formula for computation of the baud rate for different usart modes which only apply in master mode (internal clock). given the desired baud rate and fosc, the nearest inte- ger value for the spbrg register can be calculated using the formula in table 9-1. from this, the error in baud rate can be determined. example 9-1 shows the calculation of the baud rate error for the following conditions: f osc = 16 mhz desired baud rate = 9600 brgh = 0 sync = 0 example 9-1: calculating baud rate error it may be advantageous to use the high baud rate (brgh = 1) even for slower baud clocks. this is because the f osc /(16(x + 1)) equation can reduce the baud rate error in some cases. writing a new value to the spbrg register causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer over?w before output- ting the new baud rate. 9.1.1 sampling the data on the rc7/rx/dt pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the rx pin. table 9-1: baud rate formula table 9-2: registers associated with baud rate generator d esired baud rate =fosc / (64 (x + 1)) 9600 =16000000 /(64 (x + 1)) x= ? 25.042 ? = 25 calculated baud rate =16000000 / (64 (25 + 1)) = 9615 e rror = (calculated baud rate-desired baud rate ) desired baud rate = (9615 - 9600) / 9600 = 0.16% sync brgh = 0 (low speed) brgh = 1 (high speed) 0 1 (asynchronous) baud rate = f osc /(64(x+1)) (synchronous) baud rate = f osc /(4(x+1)) baud rate= f osc /(16(x+1)) na x = value in spbrg (0 to 255) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used by the brg.
pic16c63a/65b/73b/74b ds30605a-page 64 ? 1998 microchip technology inc. table 9-3: baud rates for synchronous mode table 9-4: baud rates for asynchronous mode (brgh = 0) baud rate (k) f osc = 20 mhz spbrg value (decimal) 16 mhz spbrg value (decimal) 10 mhz spbrg value (decimal) 7.15909 mhz spbrg value (decimal) kbaud % kbaud % kbaud % kbaud % 0.3 na - - na - - na - - na - - 1.2 na - - na - - na - - na - - 2.4 na - - na - - na - - na - - 9.6 na - - na - - 9.766 +1.73 255 9.622 +0.23 185 19.2 19.53 +1.73 255 19.23 +0.16 207 19.23 +0.16 129 19.24 +0.23 92 76.8 76.92 +0.16 64 76.92 +0.16 51 75.76 -1.36 32 77.82 +1.32 22 96 96.15 +0.16 51 95.24 -0.79 41 96.15 +0.16 25 94.20 -1.88 18 300 294.1 -1.96 16 307.69 +2.56 12 312.5 +4.17 7 298.3 -0.57 5 500 500 0 9 500 0 7 500 0 4 na - - high 5000 - 0 4000 - 0 2500 - 0 1789.8 - 0 low 19.53 - 255 15.625 - 255 9.766 - 255 6.991 - 255 baud rate (k) f osc = 5.0688 mhz 4 mhz spbrg value (decimal) 3.579545 mhz spbrg value (decimal) 1 mhz spbrg value (decimal) 32.768 khz spbrg value (decimal) kbaud % spbrg kbaud % kbaud % kbaud % kbaud % 0.3 na - - na - - na - - na - - 0.303 +1.14 26 1.2 na - - na - - na - - 1.202 +0.16 207 1.170 -2.48 6 2.4 na - - na - - na - - 2.404 +0.16 103 na - - 9.6 9.6 0 131 9.615 +0.16 103 9.622 +0.23 92 9.615 +0.16 25 na - - 19.2 19.2 0 65 19.231 +0.16 51 19.04 -0.83 46 19.24 +0.16 12 na - - 76.8 79.2 +3.13 15 76.923 +0.16 12 74.57 -2.90 11 83.34 +8.51 2 na - - 96 97.48 +1.54 12 1000 +4.17 9 99.43 +3.57 8 na - - na - - 300 316.8 +5.60 3 na - - 298.3 -0.57 2 na - - na - - 500 na - - na - - na - - na - - na - - high 1267 - 0 100 - 0 894.9 - 0 250 - 0 8.192 - 0 low 4.950 - 255 3.906 - 255 3.496 - 255 0.9766 - 255 0.032 - 255 baud rate (k) f osc = 20 mhz spbrg value (decimal) 16 mhz spbrg value (decimal) 10 mhz spbrg value (decimal) 7.15909 mhz spbrg value (decimal) %% %% 0.3 na - - na - - na - - na - - 1.2 1.221 +1.73 255 1.202 +0.16 207 1.202 +0.16 129 1.203 +0.23 92 2.4 2.404 +0.16 129 2.404 +0.16 103 2.404 +0.16 64 2.380 -0.83 46 9.6 9.469 -1.36 32 9.615 +0.16 25 9.766 +1.73 15 9.322 -2.90 11 19.2 19.53 +1.73 15 19.23 +0.16 12 19.53 +1.73 7 18.64 -2.90 5 76.8 78.13 +1.73 3 83.33 +8.51 2 78.13 +1.73 1 na - - 96 104.2 +8.51 2 na - - na - - na - - 300 312.5 +4.17 0 na - - na - - na - - 500 na - - na - - na - - na - - high 312.5 - 0 250 - 0 156.3 - 0 111.9 - 0 low 1.221 - 255 0.977 - 255 0.6104 - 255 0.437 - 255 baud rate (k) f osc = 5.0688 mhz 4 mhz spbrg value (decimal) 3.579545 mhz spbrg value (decimal) 1 mhz spbrg value (decimal) 32.768 khz spbrg value (decimal) % spbrg % % % % 0.3 0.31 +3.13 255 0.3005 -0.17 207 0.301 +0.23 185 0.300 +0.16 51 0.256 -14.67 1 1.2 1.2 0 65 1.202 +1.67 51 1.190 -0.83 46 1.202 +0.16 12 na - - 2.4 2.4 0 32 2.404 +1.67 25 2.432 +1.32 22 2.232 -6.99 6 na - - 9.6 9.9 +3.13 7 na - - 9.322 -2.90 5 na - - na - - 19.2 19.8 +3.13 3 na - - 18.64 -2.90 2 na - - na - - 76.8 79.2 +3.13 0 na - - na - - na - - na - - 96 na - - na - - na - - na - - na - - 300 na - - na - - na - - na - - na - - 500 na - - na - - na - - na - - na - - high 79.2 - 0 62.500 - 0 55.93 - 0 15.63 - 0 0.512 - 0 low 0.3094 - 255 3.906 - 255 0.2185 - 255 0.0610 - 255 0.0020 - 255
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 65 table 9-5: baud rates for asynchronous mode (brgh = 1) baud rate (k) f osc = 20 mhz spbrg value (decimal) 16 mhz spbrg value (deci- 10 mhz spbrg value (decimal) 7.16 mhz spbrg value (deci- %%%% 9.6 9.615 +0.16 129 9.615 +0.16 103 9.615 +0.16 64 9.520 -0.83 46 19.2 19.230 +0.16 64 19.230 +0.16 51 18.939 -1.36 32 19.454 +1.32 22 38.4 37.878 -1.36 32 38.461 +0.16 25 39.062 +1.7 15 37.286 -2.90 11 57.6 56.818 -1.36 21 58.823 +2.12 16 56.818 -1.36 10 55.930 -2.90 7 115.2 113.636 -1.36 10 111.111 -3.55 8 125 +8.51 4 111.860 -2.90 3 250 250 0 4 250 0 3 na - - na - - 625 625 0 1 na - - 625 0 0 na - - 1250 1250 0 0 na - - na - - na - - baud rate (k) f osc = 5.068 spbrg value (decimal) 4 mhz spbrg value (decimal) 3.579 mhz spbrg value (decimal) 1 mhz spbrg value (decimal) 32.768 khz spbrg value (decimal) %%%%% 9.6 9.6 0 32 na - - 9.727 +1.32 22 8.928 -6.99 6 na - - 19.2 18.645 -2.94 16 1.202 +0.17 207 18.643 -2.90 11 20.833 +8.51 2 na - - 38.4 39.6 +3.12 7 2.403 +0.13 103 37.286 -2.90 5 31.25 -18.61 1 na - - 57.6 52.8 -8.33 5 9.615 +0.16 25 55.930 -2.90 3 62.5 +8.51 0 na - - 115.2 105.6 -8.33 2 19.231 +0.16 12 111.860 -2.90 1 na - - na - - 250 na - - na - - 223.721 -10.51 0 na - - na - - 625 na - - na - - na - - na - - na - - 1250 na - - na - - na - - na - - na - -
pic16c63a/65b/73b/74b ds30605a-page 66 ? 1998 microchip technology inc. 9.2 usar t async hr onous mode in this mode, the usart uses standard non-return-to- zero (nrz) format (one start bit, eight or nine data bits and one stop bit). the most common data format is 8-bits. an on-chip dedicated 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. the usart transmits and receives the lsb ?st. the usarts transmitter and receiver are functionally independent, but use the same data format and baud rate. the baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on bit brgh (txsta<2>). parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). asynchronous mode is stopped during sleep. asynchronous mode is selected by clearing bit sync (txsta<4>). the usart asynchronous module consists of the fol- lowing important elements: baud rate generator sampling circuit asynchronous transmitter asynchronous receiver 9.2.1 usart asynchronous transmitter the usart transmitter block diagram is shown in figure 9-3. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer, txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg register (if available). once the txreg register transfers the data to the tsr register (occurs in one t cy ), the txreg register is empty and ?g bit txif (pir1<4>) is set. this interrupt can be enabled/disabled by setting/clearing enable bit txie ( pie1<4>). flag bit txif will be set regardless of the state of enable bit txie and cannot be cleared in soft- ware. it will reset only when new data is loaded into the txreg register. while ?g bit txif indicated the status of the txreg register, another bit trmt (txsta<1>) shows the status of the tsr register. status bit trmt is a read only bit which is set when the tsr register is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr reg- ister is empty. steps to follow when setting up an asynchronous trans- mission: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, set bit brgh. (section 9.1) 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, then set transmit bit tx9. 5. enable the transmission by setting bit txen, which will also set bit txif. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. load data to the txreg register (starts trans- mission). figure 9-3: usart transmit block diagram note 1: the tsr register is not mapped in data memory so it is not available to the user. note 2: flag bit txif is set when enable bit txen is set. txif txie interrupt txen baud rate clk spbrg baud rate generator tx9d msb lsb data bus txreg register tsr register (8) 0 tx9 trmt spen rc6/tx/ck pin pin buffer and control 8
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 67 figure 9-4: asynchronous transmission figure 9-5: asynchronous transmission (back to back) table 9-6: registers associated with asynchronous transmission address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0ch pir1 pspif (1) adif (2) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) adie (2) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for asynchronous transmission. note 1: portd and porte not implemented on the pic16c63a/73b, maintain as ?? 2: a/d not implemented on the pic16c63a/65b, maintain as ?? word 1 stop bit word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg word 1 brg output (shift clock) rc6/tx/ck (pin) txif bit (transmit buffer reg. empty ?g) trmt bit (transmit shift reg. empty ?g) transmit shift reg. write to txreg brg output (shift clock) rc6/tx/ck (pin) txif bit (interrupt reg. ?g) trmt bit (transmit shift reg. empty ?g) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions.
pic16c63a/65b/73b/74b ds30605a-page 68 ? 1998 microchip technology inc. 9.2.2 usart asynchronous receiver the receiver block diagram is shown in figure 9-6. the data is received on the rc7/rx/dt pin and drives the data recovery block. the data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at f osc . steps to follow when setting up an asynchronous reception: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, set bit brgh. (section 9.1). 2. enable the asynchronous serial port by clearing bit sync, and setting bit spen. 3. if interrupts are desired, then set enable bit rcie. 4. if 9-bit reception is desired, then set bit rx9. 5. enable the reception by setting bit cren. 6. flag bit rcif will be set when reception is com- plete and an interrupt will be generated if enable bit rcie was set. 7. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcreg register. 9. if any error occurred, clear the error by clearing enable bit cren. figure 9-6: usart receive block diagram figure 9-7: asynchronous reception x64 baud rate clk spbrg baud rate generator rc7/rx/dt pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 ? 64 ? 16 or stop start (8) 7 1 0 rx9 start bit bit7/8 bit1 bit0 bit7/8 bit0 stop bit start bit start bit bit7/8 stop bit rx (pin) reg rcv buffer reg rcv shift read rcv buffer reg rcreg rcif (interrupt ?g) oerr bit cren word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx input. the rcreg (receive buffer) is read after the third wo rd, causing the oerr (overrun) bit to be set.
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 69 table 9-7: registers associated with asynchronous reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0ch pir1 pspif (1) adif (2) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie (2) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for asynchronous reception. note 1: bits pspie and pspif are reserved on the pic16c63a/73b, always maintain these bits clear. 2: bits adie and adif are reserved on the pic16c63a/65b, always maintain these bits clear.
pic16c63a/65b/73b/74b ds30605a-page 70 ? 1998 microchip technology inc. 9.3 usar t sync h r onous master mode in synchronous master mode, the data is transmitted in a half-duplex manner, i.e. transmission and reception do not occur at the same time. when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit sync (txsta<4>). in addition, enable bit spen (rcsta<7>) is set in order to con?ure the rc6/tx/ck and rc7/rx/dt i/o pins to ck (clock) and dt (data) lines respectively. the master mode indicates that the processor transmits the master clock on the ck line. the master mode is entered by setting bit csrc (txsta<7>). 9.3.1 usart synchronous master transmission the usart transmitter block diagram is shown in figure 9-3. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txreg (if available). once the txreg register transfers the data to the tsr register (occurs in one tcycle), the txreg is empty and inter- rupt bit txif (pir1<4>) is set. the interrupt can be enabled/disabled by setting/clearing enable bit txie (pie1<4>). flag bit txif will be set regardless of the state of enable bit txie and cannot be cleared in soft- ware. it will reset only when new data is loaded into the txreg register. while ?g bit txif indicates the status of the txreg register, another bit trmt (txsta<1>) shows the status of the tsr register. trmt is a read only bit which is set when the tsr is empty. no inter- rupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. the tsr is not mapped in data memory so it is not available to the user. steps to follow when setting up a synchronous master transmission: 1. initialize the spbrg register for the appropriate baud rate (section 9.1). 2. enable the synchronous master serial port by setting bits sync, spen, and csrc. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, then set bit tx9. 5. enable the transmission by setting bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. table 9-8: registers associated with synchronous master transmission address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0ch pir1 pspif (1) adif (2) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) adie (2) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as '0'. shaded cells are not used for synchronous master transmission. note 1: bits pspie and pspif are reserved on the pic16c63a/73b, always maintain these bits clear. 2: bits adie and adif are reserved on the pic16c63a/65b, always maintain these bits clear.
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 71 figure 9-8: synchronous transmission figure 9-9: synchronous transmission (through txen) bit 0 bit 1 bit 7 word 1 q1q2 q3q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2 q3q4 q3q4 q1q2 q3q4 q1q2 q3q4 q1q2 q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 bit 2 bit 0 bit 1 bit 7 rc7/rx/dt pin rc6/tx/ck pin write to txreg reg txif bit (interrupt flag) trmt txen bit '1' '1' note: sync master mode; spbrg = '0'. continuous transmission of two 8-bit words word 2 trmt bit write word1 write word2 rc7/rx/dt pin rc6/tx/ck pin write to txreg reg txif bit trmt bit bit0 bit1 bit2 bit6 bit7 txen bit
pic16c63a/65b/73b/74b ds30605a-page 72 ? 1998 microchip technology inc. 9.3.2 usart synchronous master reception once synchronous mode is selected, reception is enabled by setting either enable bit sren (rcsta<5>) or enable bit cren (rcsta<4>). data is sampled on the rc7/rx/dt pin on the falling edge of the clock. if enable bit sren is set, then only a single word is received. if enable bit cren is set, the reception is continuous until cren is cleared. if both bits are set, then cren takes precedence. steps to follow when setting up a synchronous master reception: 1. initialize the spbrg register for the appropriate baud rate. (section 9.1) 2. enable the synchronous master serial port by setting bits sync, spen, and csrc. 3. ensure bits cren and sren are clear. 4. if interrupts are desired, then set enable bit rcie. 5. if 9-bit reception is desired, then set bit rx9. 6. if a single reception is required, set bit sren. for continuous reception, set bit cren. 7. interrupt ?g bit rcif will be set when reception is complete and an interrupt will be generated if enable bit rcie was set. 8. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg register. 10. if any error occurred, clear the error by clearing bit cren. table 9-9: registers associated with synchronous master reception figure 9-10: synchronous reception (master mode, sren) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0ch pir1 pspif (1) adif (2) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie (2) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used for synchronous master reception. note 1: bits pspie and pspif are reserved on the pic16c63a/73b. always maintain these bits clear. 2: bits adie and adif are reserved on the pic16c63a/65b. allways maintain these bits clear. cren bit rc7/rx/dt pin rc6/tx/ck pin write to bit sren sren bit rcif bit (interrupt) read rxreg note: timing diagram demonstrates sync master mode with bit sren = '1' and bit brgh = '0'. q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4 '0' bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 '0' q1 q2 q3 q4
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 73 9.4 usar t s ync hr onous sla ve mode synchronous slave mode differs from the master mode in the fact that the shift clock is supplied externally at the rc6/tx/ck pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in sleep mode. slave mode is entered by clearing bit csrc (txsta<7>). 9.4.1 usart synchronous slave transmit the operation of the synchronous master and slave modes are identical, except in the case of the sleep mode. if two words are written to the txreg and then the sleep instruction is executed, the following will occur: a) the ?st word will immediately transfer to the tsr register and transmit. b) the second word will remain in txreg register. c) flag bit txif will not be set. d) when the ?st word has been shifted out of tsr, the txreg register will transfer the second word to the tsr and ?g bit txif will now be set. e) if enable bit txie is set, the interrupt will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). steps to follow when setting up a synchronous slave transmission: 1. enable the synchronous slave serial port by set- ting bits sync and spen and clearing bit csrc. 2. clear bits cren and sren. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, then set bit tx9. 5. enable the transmission by setting enable bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. 9.4.2 usart synchronous slave reception the operation of the synchronous master and slave modes is identical except in the case of the sleep mode and bit sren, which is a "don't care" in slave mode. if receive is enabled by setting bit cren prior to the sleep instruction, then a word may be received during sleep. on completely receiving the word, the rsr register will transfer the data to the rcreg register and if enable bit rcie bit is set, the interrupt generated will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). steps to follow when setting up a synchronous slave reception: 1. enable the synchronous master serial port by setting bits sync and spen and clearing bit csrc. 2. if interrupts are desired, then set enable bit rcie. 3. if 9-bit reception is desired, then set bit rx9. 4. to enable reception, set enable bit cren. 5. flag bit rcif will be set when reception is com- plete. an interrupt will be generated if enable bit rcie was set. 6. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg register. 8. if any error occurred, clear the error by clearing bit cren.
pic16c63a/65b/73b/74b ds30605a-page 74 ? 1998 microchip technology inc. table 9-10: registers associated with synchronous slave transmission table 9-11: registers associated with synchronous slave reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0ch pir1 pspif (1) adif (2) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) adie (2) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used for synchronous slave transmission. note 1: bits pspie and pspif are reserved on the pic16c63a/73b. always maintain these bits clear. 2: bits adie and adif are reserved on the pic16c63a/65b. always maintain these bits clear. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0ch pir1 pspif (1) adif (2) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie (2) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used for synchronous slave reception. note 1: bits pspie and pspif are reserved on the pic16c63a/73b. always maintain these bits clear. 2: bits adie and adif are reserved on the pic16c63a/65b. always maintain these bits clear.
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 75 10.0 analog-to-digital converter (a/d) module this section applies to the pic16c73b and pic16c74b only. the analog-to-digital (a/d) converter module has ?e inputs for the pic16c73b, and eight for the pic16c74b. the a/d allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to applica- tion note an546 for use of a/d converter). the output of the sample and hold is the input into the converter, which generates the result via successive approxima- tion. the analog reference voltage is software select- able to either the devices positive supply voltage (v dd ) or the voltage level on the ra3/an3/v ref pin. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to oper- ate in sleep, the a/d conversion clock must be derived from the a/ds internal rc oscillator. additional information on the a/d module is available in the picmicro ? mid-range reference manual, (ds33023). the a/d module has three registers. these registers are: a/d result register (adres) a/d control register 0 (adcon0) a/d control register 1 (adcon1) a device reset forces all registers to their reset state. this forces the a/d module to be turned off and any conversion is aborted. the adcon0 register, shown in figure 10-1, controls the operation of the a/d module. the adcon1 regis- ter, shown in figure 10-2, con?ures the functions of the port pins. the port pins can be con?ured as ana- log inputs (ra3 can also be a voltage reference) or as digital i/o. figure 10-1: adcon0 register (address 1fh) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 adcs1 adcs0 chs2 chs1 chs0 go/done adon r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-6: adcs1:adcs0: a/d conversion clock select bits 00 = f osc /2 01 = f osc /8 10 = f osc /32 11 = f rc (clock derived from an internal rc oscillator) bit 5-3: chs2:chs0 : analog channel select bits 000 = channel 0, (ra0/an0) 001 = channel 1, (ra1/an1) 010 = channel 2, (ra2/an2) 011 = channel 3, (ra3/an3) 100 = channel 4, (ra5/an4) bit 2: go/done : a/d conversion status bit if adon = 1 1 = a/d conversion in progress (setting this bit starts the a/d conversion) 0 = a/d conversion not in progress (this bit is automatically cleared by hardware when the a/d conversion is complete) bit 1: unimplemented : read as '0' bit 0: adon : a/d on bit 1 = a/d converter module is operating 0 = a/d converter module is shutoff and consumes no operating current
pic16c63a/65b/73b/74b ds30605a-page 76 ? 1998 microchip technology inc. figure 10-2: adcon1 register (address 9fh) u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 pcfg2 pcfg1 pcfg0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-3: unimplemented: read as '0' bit 2-0: pcfg2:pcfg0 : a/d port con?uration control bits a = analog input d = digital i/o pcfg2:pcfg0 ra0 ra1 ra2 ra5 ra3 v ref 000 aaaaa v dd 001 aaaav ref ra3 010 aaaaa v dd 011 aaaav ref ra3 100 aadda v dd 101 aaddv ref ra3 11x ddddd v dd
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 77 the adres register contains the result of the a/d con- version. when the a/d conversion is complete, the result is loaded into the adres register, the go/done bit (adcon0<2>) is cleared, and a/d interrupt ?g bit adif is set. the block diagram of the a/d module is shown in figure 10-3. the value that is in the adres register is not modi?d for a power-on reset. the adres register will contain unknown data after a power-on reset. after the a/d module has been con?ured as desired, the selected channel must be acquired before the con- version is started. the analog input channels must have their corresponding tris bits selected as an input. to determine acquisition time, see section 10.1. after this acquisition time has elapsed the a/d conver- sion can be started. the following steps should be fol- lowed for doing an a/d conversion: 1. con?ure the a/d module: con?ure analog pins / voltage reference / and digital i/o (adcon1) select a/d input channel (adcon0) select a/d conversion clock (adcon0) turn on a/d module (adcon0) 2. con?ure a/d interrupt (if desired): clear adif bit set adie bit set gie bit 3. wait the required acquisition time. 4. start conversion: set go/done bit (adcon0) 5. wait for a/d conversion to complete, by either: polling for the go/done bit to be cleared or waiting for the a/d interrupt 6. read a/d result register (adres), clear bit adif if required. 7. for next conversion, go to step 1 or step 2 as required. the a/d conversion time per bit is de?ed as t ad . a minimum wait of 2t ad is required before next acquisition starts. figure 10-3: a/d block diagram (input voltage) v in v ref (reference voltage) v dd pcfg2:pcfg0 chs2:chs0 000 or 010 or 100 001 or 011 or 101 re2/an7 (1) re1/an6 (1) re0/an5 (1) ra5/an4 ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 111 110 101 100 011 010 001 000 a/d converter note 1: available on the pic16c74b only.
pic16c63a/65b/73b/74b ds30605a-page 78 ? 1998 microchip technology inc. 10.1 a/d acquisition requirements for the a/d converter to meet its speci?d accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 10-4. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ). the source impedance affects the offset voltage at the ana- log input (due to pin leakage current). the maximum recommended impedance for analog sources is 10 k w . after the analog input channel is selected (changed) this acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, t acq , see the picmicro ? mid-range reference manual, (ds33023). this equation calculates the acquisition time to within 1/2 lsb error (512 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its speci?d accuracy. figure 10-4: analog input model note: when the conversion is started, the hold- ing capacitor is disconnected from the input pin. c pin va rs anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = dac capacitance v ss 6v sampling switch 5v 4v 3v 2v 5 6 7 8 9 10 11 ( k w ) v dd = 51.2 pf 500 na legend c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 79 10.2 selecting the a /d con ver sion cloc k the a/d conversion time per bit is de?ed as t ad . the a/d conversion requires 9.5t ad per 8-bit conversion. the source of the a/d conversion clock is software selectable. the four possible options for t ad are: ?t osc ?t osc 32t osc internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time of 1.6 m s. table 10-1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. 10.3 conf iguring analog p or t pins the adcon1, trisa, and trise registers control the operation of the a/d port pins. the port pins that are desired as analog inputs must have their correspond- ing tris bits set (input). if the tris bit is cleared (out- put), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs2:chs0 bits and the tris bits. table 10-1: t ad vs. device operating frequencies note 1: when reading the port register, all pins con?ured as analog input channels will read as cleared (a low level). pins con?- ured as digital inputs, will convert an ana- log input. analog levels on a digitally con?ured input will not affect the conver- sion accuracy. note 2: analog levels on any pin that is de?ed as a digital input (including the an4:an0 pins) may cause the input buffer to con- sume current that is out of the devices speci?ation. ad clock source (t ad ) device frequency operation adcs1:adcs0 20 mhz 5 mhz 1.25 mhz 333.33 khz 2t osc 00 100 ns (2) 400 ns (2) 1.6 m s6 m s 8t osc 01 400 ns (2) 1.6 m s 6.4 m s 24 m s (3) 32t osc 10 1.6 m s 6.4 m s 25.6 m s (3) 96 m s (3) rc (5) 11 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1) legend: shaded cells are outside of recommended range. note 1: the rc source has a typical t ad time of 4 m s. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: when device frequency is greater than 1 mhz, the rc a/d conversion clock source is recommended for sleep operation only. 5: for extended voltage devices (lc), please refer to electrical speci?ations section.
pic16c63a/65b/73b/74b ds30605a-page 80 ? 1998 microchip technology inc. 10.4 a/d con ver sions 10.5 use of the ccp t rig g er an a/d conversion can be started by the ?pecial event trigger of the ccp2 module. this requires that the ccp2m3:ccp2m0 bits (ccp2con<3:0>) be pro- grammed as 1011 and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, starting the a/d conversion, and the timer1 counter will be reset to zero. timer1 is reset to automatically repeat the a/d acquisition period with minimal software overhead (moving the adres to the desired location). the appropriate analog input channel must be selected and the minimum acquisition done before the ?pecial event trigger sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), then the ?pecial event trigger will be ignored by the a/d module, but will still reset the timer1 counter. table 10-2: summary of a/d registers note: the go/done bit should not be set in the same instruction that turns on the a/d. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 0dh pir2 ccp2if ---- ---0 ---- ---0 8dh pie2 ccp2ie ---- ---0 ---- ---0 1eh adres a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/don e adon 0000 00-0 0000 00-0 9fh adcon1 pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 05h porta ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 85h trisa porta data direction register --11 1111 --11 1111 09h porte re2 re1 re0 ---- -xxx ---- -uuu 89h trise ibf obf ibov pspmode porte data direction bits 0000 -111 0000 -111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used for a/d conversion. note 1: bits pspie and pspif are reserved on the pic6c73b. always maintain these bits clear.
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 81 11.0 special features of the cpu the pic16c63a/65b/73b/74b devices have a host of features intended to maximize system reliability, mini- mize cost through elimination of external components, provide power saving operating modes and offer code protection. these are: osc selection reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) interrupts watchdog timer (wdt) sleep code protection id locations in-circuit serial programming these devices have a watchdog timer which can be shut off only through con?uration bits. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which provides a ?ed delay on power-up only, designed to keep the part in reset while the power supply stabilizes. with these two timers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up or through an interrupt. several oscillator options are also made available to allow the part to ? the application. the rc oscillator option saves system cost, while the lp crystal option saves power. a set of con?uration bits are used to select various options. additional information on special features is available in the picmicro ? mid-range reference manual, (ds33023). 11.1 c on guration bits the con?uration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device con?urations. these bits are mapped in pro- gram memory location 2007h. the user will note that address 2007h is beyond the user program memory space. in fact, it belongs to the special test/con?uration memory space (2000h - 3fffh), which can be accessed only during program- ming. figure 11-1: configuration word cp1 cp0 cp1 cp0 cp1 cp0 boden cp1 cp0 pwr te wdte fosc1 fosc0 register:config address2007h bit13 bit0 bit 13-8 cp1:cp0 : code protection bits (2) 5-4: 11 = code protection off 10 = upper half of program memory code protected 01 = upper 3/4th of program memory code protected 00 = all memory is code protected bit 7: unimplemented : read as '1' bit 6: boden : brown-out reset enable bit (1) 1 = bor enabled 0 = bor disabled bit 3: pwr te : power-up timer enable bit (1) 1 = pwrt disabled 0 = pwrt enabled bit 2: wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0: fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: enabling brown-out reset automatically enables power-up timer (pwrt) regardless of the value of bit pwr te . ensure the power-up timer is enabled anytime brown-out reset is enabled. 2: all of the cp1:cp0 pairs have to be given the same value to enable the code protection scheme listed.
pic16c63a/65b/73b/74b ds30605a-page 82 ? 1998 microchip technology inc. 11.2 oscillator con gurations 11.2.1 oscillator types the pic16cxxx can be operated in four different oscil- lator modes. the user can program two con?uration bits (fosc1 and fosc0) to select one of these four modes: lp low power crystal xt crystal/resonator hs high speed crystal/resonator rc resistor/capacitor 11.2.2 crystal oscillator/ceramic resonators in xt, lp or hs modes a crystal or ceramic resonator is connected to the osc1/clkin and osc2/clkout pins to establish oscillation (figure 11-2). the pic16cxxx oscillator design requires the use of a par- allel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers speci?a- tions. when in xt, lp or hs modes, the device can have an external clock source to drive the osc1/ clkin pin (figure 11-3). figure 11-2: crystal/ceramic resonator operation (hs, xt or lp osc configuration) figure 11-3: external clock input operation (hs, xt or lp osc configuration) table 11-1: ceramic resonators table 11-2: capacitor selection for crystal oscillator note1: see table 11-1 and table 11-2 for recom- mended values of c1 and c2. 2: a series resistor (rs) may be required for at strip cut crystals. 3: rf varies with the crystal chosen. c1 (1) c2 (1) xtal osc2 osc1 rf (3) sleep to logic pic16cxxx rs (2) internal osc1 osc2 open clock from ext. system pic16cxxx ranges tested: mode freq osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 68 - 100 pf 15 - 68 pf 15 - 68 pf 68 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 10 - 68 pf 10 - 22 pf 10 - 68 pf 10 - 22 pf these values are for design guidance only. see notes at bottom of page. resonators used: 455 khz panasonic efo-a455k04b 0.3% 2.0 mhz murata erie csa2.00mg 0.5% 4.0 mhz murata erie csa4.00mg 0.5% 8.0 mhz murata erie csa8.00mt 0.5% 16.0 mhz murata erie csa16.00mx 0.5% all resonators used did not have built-in capacitors. osc type crystal freq cap. range c1 cap. range c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 47-68 pf 47-68 pf 1 mhz 15 pf 15 pf 4 mhz 15 pf 15 pf hs 4 mhz 15 pf 15 pf 8 mhz 15-33 pf 15-33 pf 20 mhz 15-33 pf 15-33 pf these values are for design guidance only. see notes at bottom of page. crystals used 32 khz epson c-001r32.768k-a 20 ppm 200 khz std xtl 200.000khz 20 ppm 1 mhz ecs ecs-10-13-1 50 ppm 4 mhz ecs ecs-40-20-1 50 ppm 8 mhz epson ca-301 8.000m-c 30 ppm 20 mhz epson ca-301 20.000m-c 30 ppm note 1: recommended values of c1 and c2 are identical to the ranges tested (table 11-1). 2: higher capacitance increases the stability of oscillator but also increases the start-up time. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropri- ate values of external components. 4: rs may be required in hs mode, as well as xt mode, to avoid overdriving crystals with low drive level speci?ation.
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 83 11.2.3 rc oscillator for timing insensitive applications, the ?c device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resis- tor (r ext ) and capacitor (c ext ) values and the operat- ing temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal pro- cess parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c compo- nents used. figure 11-4 shows how the r/c combina- tion is connected to the pic16cxxx. figure 11-4: rc oscillator mode 11.3 reset the pic16cxxx differentiates between various kinds of reset: power-on reset (por) mclr reset during normal operation mclr reset during sleep wdt reset (during normal operation) wdt wake-up (during sleep) brown-out reset (bor) some registers are not affected in any reset condition. their status is unknown on por and unchanged in any other reset. most other registers are reset to a ?eset state on power-on reset (por), on the mclr and wdt reset, on mclr reset during sleep and brown- out reset (bor). they are not affected by a wdt wake-up, which is viewed as the resumption of normal operation. the t o and pd bits are set or cleared differ- ently in different reset situations as indicated in table 11-4. these bits are used in software to deter- mine the nature of the reset. see table 11-6 for a full description of reset states of all registers. a simpli?d block diagram of the on-chip reset circuit is shown in figure 11-5. the picmicros have a mclr noise ?ter in the mclr reset path. the ?ter will detect and ignore small pulses. it should be noted that a wdt reset does not drive mclr pin low. osc2/clkout cext rext pic16cxxx osc1 fosc/4 internal clock v dd v ss recommended values: 3 k w rext 100 k w cext > 20pf
pic16c63a/65b/73b/74b ds30605a-page 84 ? 1998 microchip technology inc. figure 11-5: simplified block diagram of on-chip reset circuit s r q external reset mclr v dd osc1 wdt module v dd rise detect ost/pwrt on-chip rc osc wdt time-out power-on reset ost 10-bit ripple counter pwrt chip_reset 10-bit ripple counter reset enable ost enable pwrt sleep note 1: this is a separate oscillator from the rc oscillator of the clkin pin. brown-out reset boden (1)
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 85 11.4 p o wer -on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected (in the range of 1.5v - 2.1v). to take advantage of the por, just tie the mclr pin directly (or through a resistor) to v dd . this will eliminate external rc components usually needed to create a power-on reset. a maximum rise time for v dd is spec- i?d (parameter d004). for a slow rise time, see figure 11-6. when the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure oper- ation. if these conditions are not met, the device must be held in reset until the operating conditions are met. brown-out reset may be used to meet the start-up con- ditions. figure 11-6: external power-on reset circuit (for slow v dd power-up) 11.5 p o wer -up timer (pwr t) the power-up timer provides a ?ed nominal time-out (parameter #33) on power-up only, from the por. the power-up timer operates on an internal rc oscillator. the chip is kept in reset as long as the pwrt is active. the pwrts time delay allows v dd to rise to an accept- able level. a con?uration bit is provided to enable/dis- able the pwrt. the power-up time delay will vary from chip to chip due to v dd , temperature and process variation. see dc parameters for details. 11.6 oscillator star t-up timer (ost) the oscillator start-up timer (ost) provides 1024 oscillator cycle (from osc1 input) delay after the pwrt delay is over (parameter #32). this ensures that the crystal oscillator or resonator has started and sta- bilized. the ost time-out is invoked only for xt, lp and hs modes and only on power-on reset or wake-up from sleep. 11.7 br o wn-out reset (bor) a con?uration bit, boden, can disable (if clear/pro- grammed) or enable (if set) the brown-out reset cir- cuitry. if v dd falls below parameter d005 for greater than parameter #35, the brown-out situation will reset the chip. a reset may not occur if v dd falls below parameter d005 for less than parameter #35. the chip will remain in brown-out reset until v dd rises above bv dd . the power-up timer will then be invoked and will keep the chip in reset an additional time delay (parameter #33). if v dd drops below bv dd while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be initial- ized. once v dd rises above bv dd , the power-up timer will execute the additional time delay. the power-up timer should always be enabled when brown-out reset is enabled. note 1: external power-on reset circuit is required only if v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k w is recommended to make sure that voltage drop across r does not violate the devices electrical speci?ation. 3: r1 = 100 w to 1 k w will limit any current ?wing into mclr from external capacitor c in the event of mclr/ v pp pin break- down due to electrostatic discharge (esd) or electrical overstress (eos). c r1 r d v dd mclr pic16cxxx
pic16c63a/65b/73b/74b ds30605a-page 86 ? 1998 microchip technology inc. 11.8 time-out sequence on power-up, the time-out sequence is as follows: first pwrt time-out is invoked after the por time delay has expired. then ost is activated. the total time-out will vary based on oscillator con?uration and the status of the pwrt. for example, in rc mode with the pwrt disabled, there will be no time-out at all. figure 11-7, figure 11-8, figure 11-9 and figure 11-10 depict time- out sequences on power-up. since the time-outs occur from the por pulse, if mclr is kept low long enough, the time-outs will expire. then bringing mclr high will begin execution immediately (figure 11-9). this is useful for testing purposes or to synchronize more than one pic16cxxx device operat- ing in parallel. table 11-5 shows the reset conditions for some special function registers, while table 11-6 shows the reset conditions for all the registers. 11.9 p o wer contr ol/status register (pcon) the power control/status register, pcon, has up to two bits, depending upon the device. bit0 is brown-out reset status bit, bor . if the boden con?uration bit is set, bor is ? on power-on reset. if the boden con?uration bit is clear, bor is unknown on power-on reset. the bor status bit is a "don't care" and is not neces- sarily predictable if the brown-out circuit is disabled (the boden con?uration bit is clear). bor must then be set by the user and checked on subsequent resets to see if it is clear, indicating a brown-out has occurred. bit1 is por (power-on reset status bit). it is cleared on a power-on reset and unaffected otherwise. the user must set this bit following a power-on reset. table 11-3: time-out in various situations table 11-4: status bits and their significance table 11-5: reset condition for special registers oscillator con?uration power-up brown-out wake-up from sleep pwr te = 0 pwr te = 1 xt, hs, lp 72 ms + 1024t osc 1024t osc 72 ms + 1024t osc 1024t osc rc 72 ms 72 ms por bor t o pd 0x11 power-on reset 0x0x illegal, t o is set on por 0xx0 illegal, pd is set on por 1011 brown-out reset 1101 wdt reset 1100 wdt wake-up 11uu mclr reset during normal operation 1110 mclr reset during sleep or interrupt wake-up from sleep condition program counter status register pcon register power-on reset 000h 0001 1xxx ---- --0x mclr reset during normal operation 000h 000u uuuu ---- --uu mclr reset during sleep 000h 0001 0uuu ---- --uu wdt reset 000h 0000 1uuu ---- --uu wdt wake-up pc + 1 uuu0 0uuu ---- --uu brown-out reset 000h 0001 1uuu ---- --u0 interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---- --uu legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. note 1: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h).
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 87 table 11-6: initialization conditions for all registers register applicable devices power-on reset, brown-out reset mclr resets wdt reset wake-up via wdt or interrupt w 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu indf 63a 65b 73b 74b n/a n/a n/a tmr0 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu pcl 63a 65b 73b 74b 0000h 0000h pc + 1 (2) status 63a 65b 73b 74b 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu porta (4) 63a 65b 73b 74b --0x 0000 --0u 0000 --uu uuuu portb (5) 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu portc (5) 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu portd (5) 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu porte (5) 63a 65b 73b 74b ---- -xxx ---- -uuu ---- -uuu pclath 63a 65b 73b 74b ---0 0000 ---0 0000 ---u uuuu intcon 63a 65b 73b 74b 0000 000x 0000 000u uuuu uuuu (1) pir1 63a 65b 73b 74b --00 0000 --00 0000 --uu uuuu (1) 63a 65b 73b 74b -000 0000 -000 0000 -uuu uuuu (1) 63a 65b 73b 74b 0-00 0000 0-00 0000 u-uu uuuu (1) 63a 65b 73b 74b 0000 0000 0000 0000 uuuu uuuu (1) pir2 63a 65b 73b 74b ---- ---0 ---- ---0 ---- ---u (1) tmr1l 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu tmr1h 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu t1con 63a 65b 73b 74b --00 0000 --uu uuuu --uu uuuu tmr2 63a 65b 73b 74b 0000 0000 0000 0000 uuuu uuuu t2con 63a 65b 73b 74b -000 0000 -000 0000 -uuu uuuu sspbuf 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu sspcon 63a 65b 73b 74b 0000 0000 0000 0000 uuuu uuuu ccpr1l 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu ccpr1h 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu ccp1con 63a 65b 73b 74b --00 0000 --00 0000 --uu uuuu rcsta 63a 65b 73b 74b 0000 -00x 0000 -00x uuuu -uuu txreg 63a 65b 73b 74b 0000 0000 0000 0000 uuuu uuuu rcreg 63a 65b 73b 74b 0000 0000 0000 0000 uuuu uuuu ccpr2l 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu ccpr2h 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu ccp2con 63a 65b 73b 74b 0000 0000 0000 0000 uuuu uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition note 1: one or more bits in intcon, pir1 and/or pir2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 11-5 for reset value for speci? condition. 4: on any device reset, these pins are con?ured as inputs. 5: this is the value that will be in the port output latch.
pic16c63a/65b/73b/74b ds30605a-page 88 ? 1998 microchip technology inc. figure 11-7: time-out sequence on power-up (mclr tied to v dd ) adres 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu adcon0 63a 65b 73b 74b 0000 00-0 0000 00-0 uuuu uu-u option_reg 63a 65b 73b 74b 1111 1111 1111 1111 uuuu uuuu trisa 63a 65b 73b 74b --11 1111 --11 1111 --uu uuuu trisb 63a 65b 73b 74b 1111 1111 1111 1111 uuuu uuuu trisc 63a 65b 73b 74b 1111 1111 1111 1111 uuuu uuuu trisd 63a 65b 73b 74b 1111 1111 1111 1111 uuuu uuuu trise 63a 65b 73b 74b 0000 -111 0000 -111 uuuu -uuu 63a 65b 73b 74b 0000 -000 0000 -000 uuuu -uuu pie1 63a 65b 73b 74b --00 0000 --00 0000 --uu uuuu 63a 65b 73b 74b 0-00 0000 0-00 0000 u-uu uuuu 63a 65b 73b 74b -000 0000 -000 0000 -uuu uuuu 63a 65b 73b 74b 0000 0000 0000 0000 uuuu uuuu pie2 63a 65b 73b 74b ---- ---0 ---- ---0 ---- ---u pcon 63a 65b 73b 74b ---- --0q ---- --uq ---- --uq pr2 63a 65b 73b 74b 1111 1111 1111 1111 1111 1111 sspadd 63a 65b 73b 74b 0000 0000 0000 0000 uuuu uuuu sspstat 63a 65b 73b 74b 0000 0000 0000 0000 uuuu uuuu txsta 63a 65b 73b 74b 0000 -010 0000 -010 uuuu -uuu spbrg 63a 65b 73b 74b 0000 0000 0000 0000 uuuu uuuu adcon1 63a 65b 73b 74b ---- -000 ---- -000 ---- -uuu table 11-6: initialization conditions for all registers (cont.d) register applicable devices power-on reset, brown-out reset mclr resets wdt reset wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition note 1: one or more bits in intcon, pir1 and/or pir2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 11-5 for reset value for speci? condition. 4: on any device reset, these pins are con?ured as inputs. 5: this is the value that will be in the port output latch. t pwrt t ost v dd mclr internal por pwr t time-out ost time-out internal reset
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 89 figure 11-8: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 11-9: time-out sequence on power-up (mclr not tied to v dd ): case 2 figure 11-10: slow rise time (mclr tied to v dd ) t pwrt t ost v dd mclr internal por pwr t time-out ost time-out internal reset v dd mclr internal por pwr t time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwr t time-out ost time-out internal reset 0v 1v 5v t pwrt t ost
pic16c63a/65b/73b/74b ds30605a-page 90 ? 1998 microchip technology inc. 11.10 interrupts the pic16cxx family has up to 12 sources of interrupt. the interrupt control register (intcon) records individ- ual interrupt requests in ?g bits. it also has individual and global interrupt enable bits. a global interrupt enable bit, gie (intcon<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. when bit gie is enabled, and an interrupts ?g bit and mask bit are set, the interrupt will vector immediately. individual interrupts can be dis- abled through their corresponding enable bits in vari- ous registers. individual interrupt bits are set regardless of the status of the gie bit. the gie bit is cleared on reset. the ?eturn from interrupt instruction, retfie , exits the interrupt routine as well as sets the gie bit, which re-enables interrupts. the rb0/int pin interrupt, the rb port change inter- rupt and the tmr0 over?w interrupt ?gs are con- tained in the intcon register. the peripheral interrupt ?gs are contained in the spe- cial function registers pir1 and pir2. the correspond- ing interrupt enable bits are contained in special function registers pie1 and pie2, and the peripheral interrupt enable bit is contained in special function reg- ister intcon. when an interrupt is responded to, the gie bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the pc is loaded with 0004h. once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt ?g bits. the interrupt ?g bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. for external interrupt events, such as the int pin or portb change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends when the interrupt event occurs. the latency is the same for one or two cycle instructions. individual interrupt ?g bits are set regardless of the status of their corresponding mask bit or the gie bit. figure 11-11: interrupt logic note: individual interrupt ?g bits are set regard- less of the status of their corresponding mask bit or the gie bit. pspif pspie adif adie rcif rcie txif txie sspif sspie ccp1if ccp1ie tmr2if tmr2ie tmr1if tmr1ie t0if t0ie intf inte rbif rbie gie peie wake-up (if in sleep mode) interrupt to cpu ccp2ie ccp2if the following table shows which devices have which interrupts. device t0if intf rbif pspif adif rcif txif sspif ccp1if tmr2if tmr1if ccp2if pic16c63a yes yes yes - - yes yes yes yes yes yes yes pic16c65b yes yes yes yes - yes yes yes yes yes yes yes pic16c73b yes yes yes - yes yes yes yes yes yes yes yes pic16c74b yes yes yes yes yes yes yes yes yes yes yes yes
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 91 11.10.1 int interrupt external interrupt on rb0/int pin is edge triggered; either rising if bit intedg (option_reg<6>) is set, or falling, if the intedg bit is clear. when a valid edge appears on the rb0/int pin, ?g bit intf (intcon<1>) is set. this interrupt can be disabled by clearing enable bit inte (intcon<4>). flag bit intf must be cleared in software in the interrupt service rou- tine before re-enabling this interrupt. the int interrupt can wake-up the processor from sleep, if bit inte was set prior to going into sleep. the status of global inter- rupt enable bit gie decides whether or not the proces- sor branches to the interrupt vector following wake-up. see section 11.13 for details on sleep mode. 11.10.2 tmr0 interrupt an over?w (ffh ? 00h) in the tmr0 register will set ?g bit t0if (intcon<2>). the interrupt can be enabled/disabled by setting/clearing enable bit t0ie (intcon<5>). (section 4.0) 11.10.3 portb intcon change an input change on portb<7:4> sets ?g bit rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit rbie (intcon<4>). (section 3.2) 11.11 conte xt sa ving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users may wish to save key reg- isters during an interrupt, i.e., w register and status register. this will have to be implemented in software. example 11-1 stores and restores the w and status registers. the register, w_temp, must be de?ed in each bank and must be de?ed at the same offset from the bank base address (i.e., if w_temp is de?ed at 0x20 in bank 0. it must also be de?ed at 0xa0 in bank 1). the example: a) stores the w register. b) stores the status register in bank 0. c) stores the pclath register. d) executes the interrupt service routine code (user-generated). e) restores the status register (and bank select bit). f) restores the w and pclath registers. example 11-1: saving status, w, and pclath registers in ram movwf w_temp ;copy w to temp register, could be bank one or zero swapf status,w ;swap status to be saved into w clrf status ;bank 0, regardless of current bank, clears irp,rp1,rp0 movwf status_temp ;save status to bank zero status_temp register movf pclath, w ;only required if using pages 1, 2 and/or 3 movwf pclath_temp ;save pclath into w clrf pclath ;page zero, regardless of current page bcf status, irp ;return to bank 0 movf fsr, w ;copy fsr to w movwf fsr_temp ;copy fsr from w to fsr_temp : :(isr) : movf pclath_temp, w ;restore pclath movwf pclath ;move w into pclath swapf status_temp,w ;swap status_temp register into w ;(sets bank to original state) movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w
pic16c63a/65b/73b/74b ds30605a-page 92 ? 1998 microchip technology inc. 11.12 w atc hdog timer (wdt) the watchdog timer is a free running on-chip rc oscil- lator, which does not require any external components. this rc oscillator is separate from the rc oscillator of the osc1/clkin pin. that means that the wdt will run, even if the clock on the osc1/clkin and osc2/ clkout pins of the device has been stopped, for example, by execution of a sleep instruction. during normal operation, a wdt time-out generates a device reset (watchdog timer reset). if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation (watch- dog timer wake-up). the t o bit in the status register will be cleared upon a watchdog timer time-out. the wdt can be permanently disabled by clearing con?uration bit wdte (section 11.1). wdt time-out period values may be found in the elec- trical speci?ations section under parameter #31. val- ues for the wdt prescaler (actually a postscaler, but shared with the timer0 prescaler) may be assigned using the option_reg register. . figure 11-12: watchdog timer block diagram figure 11-13: summary of watchdog timer registers note: the clrwdt and sleep instructions clear the wdt and the postscaler if assigned to the wdt, and prevent it from timing out and generating a device reset condition. note: when a clrwdt instruction is executed and the prescaler is assigned to the wdt, the prescaler count will be cleared, but the prescaler assignment is not changed. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2007h con?. bits (1) boden (1) cp1 cp0 pwr te (1) wdte fosc1 fosc0 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 legend: shaded cells are not used by the watchdog timer. note 1: see figure 11-1 for operation of these bits. from tmr0 clock source (figure 4-2) to tmr0 (figure 4-2) postscaler wdt timer wdt enable bit 0 1 m u x psa 8 - to - 1 mux ps2:ps0 0 1 mux psa wdt time-out note: psa and ps2:ps0 are bits in the option_reg register. 8
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 93 11.13 p o wer -do wn mode (sleep) power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the pd bit (status<3>) is cleared, the t o (status<4>) bit is set, and the oscillator driver is turned off. the i/o ports maintain the status they had, before the sleep instruction was executed (driving high, low, or hi-impedance). for lowest current consumption in this mode, place all i/o pins at either v dd , or v ss , ensure no external cir- cuitry is drawing current from the i/o pin, power-down the a/d, disable external clocks. pull all i/o pins, that are hi-impedance inputs, high or low externally to avoid switching currents caused by ?ating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on-chip pull-ups on portb should be considered. the mclr pin must be at a logic high level (v ihmc ). 11.13.1 wake-up from sleep the device can wake up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from int pin, rb port change, or some peripheral interrupts. external mclr reset will cause a device reset. all other events are considered a continuation of program execution and cause a "wake-up". the t o and pd bits in the status register can be used to determine the cause of device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the t o bit is cleared if a wdt time-out occurred (and caused wake-up). the following peripheral interrupts can wake the device from sleep: 1. psp read or write. 2. tmr1 interrupt. timer1 must be operating as an asynchronous counter. 3. ccp capture mode interrupt. 4. special event trigger (timer1 in asynchronous mode using an external clock). 5. ssp (start/stop) bit detect interrupt. 6. ssp transmit or receive in slave mode (spi/i 2 c). 7. usart rx or tx (synchronous slave mode). 8. a/d conversion (when a/d clock source is rc). other peripherals cannot generate interrupts since dur- ing sleep, no on-chip clocks are present. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the inter- rupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. 11.13.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt ?g bit set, one of the following will occur: if the interrupt occurs before the execution of a sleep instruction, the sleep instruction will com- plete as a nop. therefore, the wdt and wdt postscaler will not be cleared, the t o bit will not be set and pd bits will not be cleared. if the interrupt occurs during or after the execu- tion of a sleep instruction, the device will immedi- ately wake up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt postscaler will be cleared, the t o bit will be set and the pd bit will be cleared. even if the ?g bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop. to ensure that the wdt is cleared, a clrwdt instruc- tion should be executed before a sleep instruction.
pic16c63a/65b/73b/74b ds30605a-page 94 ? 1998 microchip technology inc. figure 11-14: wake-up from sleep through interrupt 11.14 pr ogram v eri cation/code pr otection if the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for veri?ation purposes. 11.15 id locations four memory locations (2000h - 2003h) are designated as id locations where the user can store checksum or other code-identi?ation numbers. these locations are not accessible during normal execution but are read- able and writable during program/verify. it is recom- mended that only the 4 least signi?ant bits of the id location are used. for rom devices, these values are submitted along with the rom code. 11.16 in-cir cuit serial pr ogramming pic16cxxx microcontrollers can be serially pro- grammed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground and the programming volt- age. this allows customers to manufacture boards with unprogrammed devices, and then program the micro- controller just before shipping the product. this also allows the most recent ?mware or a custom ?mware to be programmed. for complete details of serial programming, please refer to the in-circuit serial programming (icsp) guide, (ds30277b). q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout(4) int pin intf ?g (intcon<1>) gie bit (intcon<7>) instr uction flo w pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (note 2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024t osc (drawing not to scale) this delay will not be there for rc osc mode. 3: gie = '1' assumed. in this case after wake- up, the processor jumps to the interrupt routine. if gie = '0', execution will co ntinue in-line. 4: clkout is not available in these osc modes, but shown here for timing reference. note: microchip technology does not recom- mend code protecting windowed devices.
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 95 12.0 instruction set summary each pic16cxxx instruction is a 14-bit word divided into an opcode which speci?s the instruction type and one or more operands which further specify the operation of the instruction. the pic16cxx instruction set summary in table 12-2 lists byte-oriented , bit-ori- ented , and literal and control operations. table 12-1 shows the opcode ?ld descriptions. for byte-oriented instructions, 'f' represents a ?e reg- ister designator and 'd' represents a destination desig- nator. the ?e register designator speci?s which ?e register is to be used by the instruction. the destination designator speci?s where the result of the operation is to be placed. if 'd' is zero, the result is placed in the w register. if 'd' is one, the result is placed in the ?e register speci?d in the instruction. for bit-oriented instructions, 'b' represents a bit ?ld designator which selects the number of the bit affected by the operation, while 'f' represents the number of the ?e in which the bit is located. for literal and control operations, 'k' represents an eight or eleven bit constant or literal value. table 12-1: opcode field descriptions the instruction set is highly orthogonal and is grouped into three basic categories: byte-oriented operations bit-oriented operations literal and control operations all instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles with the second cycle executed as a nop. one instruc- tion cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 m s. if a conditional test is true or the program counter is changed as a result of an instruc- tion, the instruction execution time is 2 m s. table 12-2 lists the instructions recognized by the mpasm assembler. figure 12-1 shows the general formats that the instruc- tions can have. all examples use the following format to represent a hexadecimal number: 0xhh where h signi?s a hexadecimal digit. figure 12-1: general format for instructions a description of each instruction is available in the picmicro ? mid-range reference manual, (ds33023). field description f register ?e address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit ?e register k literal ?ld, constant data or label x don't care location (= 0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip technology software tools. d destination select; d = 0: store result in w, d = 1: store result in ?e register f. default is d = 1 pc program counter to time-out bit pd power-down bit note: to maintain upward compatibility with future pic16cxxx products, do not use the option and tris instructions. byte-oriented ?e register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit ?e register address bit-oriented ?e register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit ?e register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only
pic16c63a/65b/73b/74b ds30605a-page 96 ? 1998 microchip technology inc. table 12-2: pic16cxxx instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z t o , pd z t o , pd c,dc,z z note 1: when an i/o register is modi?d as a function of itself ( e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin con?ured as input and is driven low by an external device, the data will be written back with a '0'. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modi?d or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop.
pic16c62x(a) ? 1998 microchip technology inc. ds30605a-page 97 13.0 development support 13.1 de velopme nt t ools the picmicr o? microcontrollers are supported with a full range of hardware and software development tools: picmaster a /picmaster ce real-time in-circuit emulator icepic ? low-cost pic16c5x and pic16cxxx in-circuit emulator pro mate a ii universal programmer picstart a plus entry-level prototype programmer picdem-1 low-cost demonstration board picdem-2 low-cost demonstration board picdem-3 low-cost demonstration board mpasm assembler mplab ? sim software simulator mplab-c17 (c compiler) fuzzy logic development system ( fuzzy tech a - mp) 13.2 picmaster: high p erf ormance univer sal in-cir cuit em ulator with mplab ide the picmaster universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the pic14c000, pic12cxxx, pic16c5x, pic16cxxx and pic17cxx families. picmaster is supplied with the mplab ? integrated development environment (ide), which allows editing, ?ake and download, and source debugging from a single environment. interchangeable target probes allow the system to be easily recon?ured for emulation of different proces- sors. the universal architecture of the picmaster allows expansion to support all new microchip micro- controllers. the picmaster emulator system has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. the pc compatible 386 (and higher) machine platform and microsoft windows a 3.x environment were chosen to best make these fea- tures available to you, the end user. a ce compliant version of picmaster is available for european union (eu) countries. 13.3 icepic: lo w-cost picmicr o in-cir cuit em ulator icepic is a low-cost in-circuit emulator solution for the microchip pic12cxxx, pic16c5x and pic16cxxx families of 8-bit otp microcontrollers. icepic is designed to operate on pc-compatible machines ranging from 286-at a through pentium ? based machines under windows 3.x environment. icepic features real time, non-intrusive emulation. 13.4 pr o ma te ii: univer sal pr ogrammer the pro mate ii universal programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as pc-hosted mode. pro mate ii is ce compliant. the pro mate ii has programmable v dd and v pp supplies which allows it to verify programmed memory at v dd min and v dd max for maximum reliability. it has an lcd display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand- alone mode the pro mate ii can read, verify or pro- gram pic12cxxx, pic14c000, pic16c5x, pic16cxxx and pic17cxx devices. it can also set con?uration and code-protect bits in this mode. 13.5 picst ar t plus entr y le vel de velopment system the picstart programmer is an easy-to-use, low-cost prototype programmer. it connects to the pc via one of the com (rs-232) ports. mplab integrated development environment software makes using the programmer simple and ef?ient. picstart plus is not recommended for production programming. picstart plus supports all pic12cxxx, pic14c000, pic16c5x, pic16cxxx and pic17cxx devices with up to 40 pins. larger pin count devices such as the pic16c923, pic16c924 and pic17c756 may be sup- ported with an adapter socket. picstart plus is ce compliant.
pic16c62x(a) ds30605a-page 98 ? 1998 microchip technology inc. 13.6 picdem-1 lo w-cost picmicr o demonstration boar d the picdem-1 is a simple board which demonstrates the capabilities of s e v eral of microchip s microcontrol- ler s . the microcontrollers suppo r ted are : pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44 . all necessa r y hard w are and soft w are is included to r un basic demo program s . the users can program the sample micro controllers pr o vided with the picdem-1 board, on a p r o m a te ii or pics t a r t -plus programme r , and easily test r m- w ar e . the user can also connect the picdem-1 board to the picmaster emulator and d o wn load the r m w are to the emulator f or testing . additional pro- totype area is a v aila b le f or the user to b uild some addi- tional hard w are and connect it to the microcontroller so c k et(s) . some of the f eatures include an rs-232 inter f ac e , a potentiometer f or simulated analog input, push- b utton s witches and eight leds connected to po r t b . 13.7 picdem-2 lo w-cost pic16cx x x demonstration boar d the picdem-2 is a simple demonstration board that suppo r ts the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcon troller s . all the necessa r y hard w are and soft w are is included to r un the basic demonstration program s . the user can program the sample microcontrollers pr o vided with the picdem-2 board, on a p r o m a te ii pro- grammer or pics t a r t -plu s , and easily test r m w ar e . the picmaster emulator m a y also be used with the picdem-2 board to test r m w ar e . additional prototype area has been pr o vided to the user f or adding addi- tional hard w are and connecting it to the microcontroller so c k et(s) . some of the f eatures include a rs-232 inter- f ac e , push- b utton s witche s , a potentiometer f or simu- lated analog input, a se r ial eep r om to demonstrate usage of the i 2 c b us and separate headers f or connec- tion to an lcd module and a k e ypad. 13.8 picdem-3 lo w-cost pic16cxxx demonstration boar d the picdem-3 is a simple demonstration board that suppo r ts the pic16c923 and pic16c924 in the plcc pa c kag e . i t will also suppo r t future 44-pin plcc microcontrollers with a lcd modul e . all the neces- sa r y hard w are and soft w are is included to r un the basic demonstration program s . the user can pro- gram the sample microcontrollers pr o vided with the picdem-3 board, on a p r o m a te ii program- mer or pics t a r t plus with an adapter so c k et, and easily test r m w ar e . the picmaster emulator m a y also be used with the picdem-3 board to test r m- w ar e . additional prototype area has been pr o vided to the user f or adding hard w are and connecting it to the microcontroller so c k et(s) . some of the f eatures include an rs-232 inter f ac e , push- b utton s witche s , a potenti- ometer f or simulated analog input, a the r mistor and separate headers f or connection to an e xte r nal lcd module and a k e ypad . also pr o vided on the picdem-3 board is an lcd panel, with 4 commons and 12 seg- ment s , that is capa b le of displ a ying tim e , temperature and d a y of the week . the picdem-3 pr o vides an addi- tional rs-232 inter f ace an d wind o ws 3.1 soft w are f o r sh o wing the demultipl ex ed lcd signals on a p c . a sim- ple se r ial inter f ace all o ws the user to const r uct a hard- w are demultipl ex er f or the lcd signal s . 13.9 mplab integrated de velopment en vir onment software the mplab ide soft w are b r ings an ease of soft w are d e v elopment pr e viously unseen in the 8-bit microcon- troller ma r k et . mplab is a wind o ws based application which contains: a full f eatured editor three operating modes - editor - emulator - simulator a project manager customiza b le tool bar and k e y mapping a status bar with project in f o r mation extensi v e on-line help mplab all o ws y ou to: edit y our source ?es (either assem b ly o r ?? one touch assem b le (or compile) and d o wnload to picmicro tools (automatically updates all project in f o r mation) de b ug using: - source ?es - absolute listing ?e t rans f er data dynamically via dde (soon to be replaced b y ole) run up to f our emulators on the same pc the ability to use mplab with microchip s simulator all o ws a consistent plat f o r m and the ability to easily s witch from the l o w cost simulator to the full f eatured emulator with minimal retraining due to d e v elopment tool s . 13.10 assemb ler (mp asm) the m p asm uni v ersal macro assem b ler is a pc-hosted symbolic assem b le r . it suppo r ts all micro- controller se r ies including the pic12c5xx, pic14000, pic16c5x, pic16cxxx, and pic17cxx f amilie s . m p asm of f ers full f eatured macro capabilitie s , condi- tional assem b l y , and s e v eral source and listing f o r mat s . it generates v a r ious object code f o r mats to suppo r t microchip's d e v elopment tools as well as third pa r ty programmer s . m p asm all o ws full symbolic de b ugging from picmaster, microchip s uni v ersal emulator system.
pic16c62x(a) ? 1998 microchip technology inc. ds30605a-page 99 mpasm has the following features to assist in develop- ing software for speci? use applications. provides translation of assembler source code to object code for all microchip microcontrollers. macro assembly capability. produces all the ?es (object, listing, symbol, and special) required for symbolic debug with microchips emulator systems. supports hex (default), decimal and octal source and listing formats. mpasm provides a rich directive language to support programming of the picmicro. directives are helpful in making the development of your assemble source code shorter and more maintainable. 13.11 software sim ulator (mplab-sim) the mplab-sim software simulator allows code development in a pc host environment. it allows the user to simulate the picmicro series microcontrollers on an instruction level. on any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. the input/output radix can be set by the user and the exe- cution can be performed in; single step, execute until break, or in a trace mode. mplab-sim fully supports symbolic debugging using mplab-c and mpasm. the software simulator offers the low cost ?xibility to develop and debug code out- side of the laboratory environment making it an excel- lent multi-project software development tool. 13.12 c compiler ( mplab-c 17 ) the mplab-c code development system is a complete ? compiler and integrated development environment for microchips pic17cxxx family of microcontrollers. the compiler provides powerful inte- gration capabilities and ease of use not found with other compilers. for easier source level debugging, the compiler pro- vides symbol information that is compatible with the mplab ide memory display. 13.13 fuzzy logic de velopment system ( fuzzy tech-mp) fuzzy tech-mp fuzzy logic development tool is avail- able in two versions - a low cost introductory version, mp explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzy tech-mp, edition for imple- menting more complex systems. both versions include microchips fuzzy lab ? demon- stration board for hands-on experience with fuzzy logic systems implementation. 13.14 mp-drivew a y ? ?application code generator mp-driveway is an easy-to-use windows-based appli- cation code generator. with mp-driveway you can visually con?ure all the peripherals in a picmicro device and, with a click of the mouse, generate all the initialization and many functional code modules in c language. the output is fully compatible with micro- chips mplab-c c compiler. the code produced is highly modular and allows easy integration of your own code. mp-driveway is intelligent enough to maintain your code through subsequent code generation. 13.15 seev al a ev aluation and pr ogramming system the seeval seeprom designers kit supports all microchip 2-wire and 3-wire serial eeproms. the kit includes everything necessary to read, write, erase or program special features of any microchip seeprom product including smart serials ? and secure serials. the total endurance ? disk is included to aid in trade-off analysis and reliability calculations. the total kit can signi?antly reduce time-to-market and result in an optimized system. 13.16 k ee l oq a ev aluation and pr ogramming t ools k ee l oq evaluation and programming tools support microchips hcs secure data products. the hcs eval- uation kit includes an lcd display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters.
pic16c62x(a) ds30605a-page 100 1998 microchip technology inc. table 13-1 development tools from microchip pic12c5xx pic14000 pic16c5x pic16cxxx pic16c6x pic16c7xx pic16c8x pic16c9xx pic17c4x pic17c7xx 24cxx 25cxx 93cxx hcsxxx emulator products picmaster a / picmaster-ce in-circuit emulator (pic17c75x only) mplab-ice icepic ? low-cost in-circuit emulator software products mplab ? integrated development environment mplab ? c17 compiler fuzzy tech a -mp explorer/edition fuzzy logic dev. tool mp-driveway ? applications code generator total endurance ? software model programmers picstart a plus low-cost universal dev. kit pro mate a ii universal programmer keeloq a programmer demo boards seeval a designers kit picdem-1 picdem-2 picdem-3
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. preliminary ds30605a-page 101 14.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ........... .-55?c to +125?c storage temperature ............................................................................................................ .................. -65?c to +150?c voltage on any pin with respect to v ss (except v dd , mclr , and ra4).......................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +7.5v voltage on mclr with respect to v ss (note 2).......................................................................................... 0v to +13.25v voltage on ra4 with respect to vss ............................................................................................. .................. 0v to +8.5v total power dissipation (note 1)............................................................................................... .................................1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) .............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by porta, portb, and porte (note 3) (combined)....................................................200 ma maximum current sourced by porta, portb, and porte (note 3) (combined) ..............................................200 ma maximum current sunk by portc and portd (note 3) (combined) ..................................................................200 ma maximum current sourced by portc and portd (note 3) (combined) .............................................................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v o l x i ol ) note 2: voltage spikes below v ss at the mclr /v pp pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 w should be used when applying a ?ow level to the mclr /v pp pin rather than pulling this pin directly to v ss . note 3: portd and porte not available on the pic16c63a/73b. table 14-1: cross reference of device specs for oscillator modes and frequencies of operation (commercial devices) ? notice: stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. osc pic16c63a-04 pic16c65b-04 pic16c73b-04 pic16c74b-04 pic16c63a-20 pic16c65b-20 pic16c73b-20 pic16c74b-20 pic16lc63a-04 pic16lc65b-04 pic16lc73b-04 pic16lc74b-04 windowed (jw) devices rc v dd : 4.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 2.5v to 5.5v i dd : 3.8 ma max. at 3v i pd : 5 m a max. at 3v freq: 4 mhz max. v dd : 2.5v to 5.5v i dd : 3.8 ma max. at 3v i pd : 5 m a max. at 3v freq: 4 mhz max. xt v dd : 4.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 2.5v to 5.5v i dd : 3.8 ma max. at 3v i pd : 5 m a max. at 3v freq: 4 mhz max. v dd : 2.5v to 5.5v i dd : 3.8 ma max. at 3v i pd : 5 m a max. at 3v freq: 4 mhz max. hs v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v not recommended for use in hs mode v dd : 4.5v to 5.5v i dd : 13.5 ma typ. at 5.5v i dd : 20 ma max. at 5.5v i dd : 20 ma max. at 5.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v freq: 4 mhz max. freq: 20 mhz max. freq: 20 mhz max. lp v dd : 4.0v to 5.5v i dd : 52.5 m a typ. at 32 khz, 4.0v i pd : 0.9 m a typ. at 4.0v freq: 200 khz max. not recommended for use in lp mode v dd : 2.5v to 5.5v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5 m a max. at 3.0v freq: 200 khz max. v dd : 2.5v to 5.5v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5 m a max. at 3.0v freq: 200 khz max. the shaded sections indicate oscillator selections which are tested for functionality, but not for min/max speci?ations. it is recom- mended that the user select the device type that ensures the speci?ations required.
pic16c63a/65b/73b/74b ds30605a-page 102 preliminary ? 1998 microchip technology inc. 14.1 dc characteristics: pic16c63a/65b/73b/74b-04 (commercial, industrial, extended) pic16c6a/65b/73b/74b-20 (commercial, industrial, extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0?c t a +70?c for commercial -40?c t a +85?c for industrial -40?c t a +125?c for extended param no. sym characteristic min typ? max units conditions d001 d001a v dd supply voltage 4.0 4.5 v bor * - - - 5.5 5.5 5.5 v v v xt, rc and lp osc mode hs osc mode bor enabled (note 7) d002* v dr ram data retention voltage (note 1) - 1.5 - v d003 v por v dd start voltage to ensure internal power-on reset signal -v ss - v see section on power-on reset for details d004* d004a* s vdd v dd rise rate to ensure internal power-on reset signal 0.05 tbd - - - - v/ms pwrt enabled (pwr te bit clear) pwrt disabled (pwr te bit set) see section on power-on reset for details d005 v bor brown-out reset voltage trip point 3.65 - 4.35 v boden bit set d010 d013 i dd supply current (note 2, 5) - - 2.7 10 5 20 ma ma xt, rc osc modes f osc = 4 mhz, v dd = 5.5v (note 4) hs osc mode f osc = 20 mhz, v dd = 5.5v d020 d021 d021b i pd power-down current (note 3, 5) - - - - 10.5 1.5 1.5 2.5 42 16 19 19 m a m a m a m a v dd = 4.0v, wdt enabled,-40 c to +85 c v dd = 4.0v, wdt disabled, 0 c to +70 c v dd = 4.0v, wdt disabled,-40 c to +85 c v dd = 4.0v, wdt disabled,-40 c to +125 c d022* d022a* d i wdt d i bor module differential current (note 6) watchdog timer brown-out reset - - 6.0 350 20 425 m a m a wdte bit set, v dd = 4.0v boden bit set, v dd = 5.0v * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc mode, current through rext is not included. the current through the resistor can be estimated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the speci?ation. this value is from charac- terization and is for design guidance only. this is not tested. 6: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: when bor is enabled, the device will operate correctly until the v bor voltage trip point is reached.
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. preliminary ds30605a-page 103 14.2 dc characteristics: pic16lc63a/65b/73b/74b-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0?c t a +70?c for commercial -40?c t a +85?c for industrial param no. sym characteristic min typ? max units conditions d001 v dd supply voltage 2.5 v bor * - - 5.5 5.5 v v lp, xt, rc osc modes (dc - 4 mhz) bor enabled (note 7) d002* v dr ram data retention voltage (note 1) - 1.5 - v d003 v por v dd start voltage to ensure internal power-on reset signal -v ss - v see section on power-on reset for details d004* d004a* s vdd v dd rise rate to ensure internal power-on reset signal 0.05 tbd - - - - v/ms pwrt enabled (pwr te bit clear) pwrt disabled (pwr te bit set) see section on power-on reset for details d005 v bor brown-out reset voltage trip point 3.65 - 4.35 v boden bit set d010 d010a i dd supply current (note 2, 5) - - 2.0 22.5 3.8 48 ma m a xt, rc osc modes f osc = 4 mhz, v dd = 3.0v (note 4) lp osc mode f osc = 32 khz, v dd = 3.0v, wdt disabled d020 d021 d021a i pd power-down current (note 3, 5) - - - 7.5 0.9 0.9 30 5 5 m a m a m a v dd = 3.0v, wdt enabled, -40 c to +85 c v dd = 3.0v, wdt disabled, 0 c to +70 c v dd = 3.0v, wdt disabled, -40 c to +85 c d022* d022a* d i wdt d i bor module differential current (note 6) watchdog timer brown-out reset - - 6.0 350 20 425 m a m a wdte bit set, v dd = 4.0v boden bit set, v dd = 5.0v * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc mode, current through rext is not included. the current through the resistor can be estimated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the speci?ation. this value is from charac- terization and is for design guidance only. this is not tested. 6: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: when bor is enabled, the device will operate correctly until the v bor voltage trip point is reached..
pic16c63a/65b/73b/74b ds30605a-page 104 preliminary ? 1998 microchip technology inc. 14.3 dc characteristics: pic16c63a/65b/73b/74b-04 (commercial, industrial, extended) pic16c63a/65b/73b/74b-20 (commercial, industrial, extended) pic16lc63a/65b/73b/74b-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0?c t a +70?c for commercial -40?c t a +85?c for industrial -40?c t a +125?c for extended operating voltage v dd range as described in dc spec section 14.1 and section 14.2 param no. sym characteristic min typ? max units conditions input low voltage v il i/o ports d030 d030a with ttl buffer v ss v ss - - 0.15v dd 0.8v v v for entire v dd range 4.5v v dd 5.5v d031 with schmitt trigger buffer v ss - 0.2v dd v d032 mclr , osc1 (in rc mode) vss - 0.2v dd v d033 osc1 (in xt, hs and lp modes) vss - 0.3v dd v note1 input high voltage v ih i/o ports - d040 with ttl buffer 2.0 - v dd v 4.5v v dd 5.5v d040a 0.25v dd + 0.8v -v dd v for entire v dd range d041 with schmitt trigger buffer 0.8v dd -v dd v for entire v dd range d042 mclr 0.8v dd -v dd v d042a osc1 (xt, hs and lp modes) 0.7v dd -v dd v note1 d043 osc1 (in rc mode) 0.9v dd -v dd v input leakage current (notes 2, 3) d060 i il i/o ports - - 1 m a vss v pin v dd , pin at hi-impedance d061 mclr , ra4/t0cki - - 5 m a vss v pin v dd d063 osc1 - - 5 m a vss v pin v dd , xt, hs and lp osc modes d070 i purb portb weak pull-up current 50 250 400 m av dd = 5v, v pin = v ss output low voltage d080 v ol i/o ports - - 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c - - 0.6 v i ol = 7.0 ma, v dd = 4.5v, -40 c to +125 c d083 osc2/clkout (rc osc mode) - - 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c - - 0.6 v i ol = 1.2 ma, v dd = 4.5v, -40 c to +125 c * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note1: in rc oscillator mode, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the picmi- cro be driven with external clock in rc mode. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input volt- ages. 3: negative current is de?ed as current sourced by the pin.
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. preliminary ds30605a-page 105 output high voltage d090 v oh i/o ports (note 3) v dd -0.7 - - v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c v dd -0.7 - - v i oh = -2.5 ma, v dd = 4.5v, -40 c to +125 c d092 osc2/clkout (rc osc mode) v dd -0.7 - - v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c v dd -0.7 - - v i oh = -1.0 ma, v dd = 4.5v, -40 c to +125 c d150* v od open-drain high voltage - - 8.5 v ra4 pin capacitive loading specs on output pins d100 c osc2 osc2 pin - - 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 c io all i/o pins and osc2 (in rc mode) - - 50 pf d102 cb scl, sda in i 2 c mode - - 400 pf dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0?c t a +70?c for commercial -40?c t a +85?c for industrial -40?c t a +125?c for extended operating voltage v dd range as described in dc spec section 14.1 and section 14.2 param no. sym characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note1: in rc oscillator mode, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the picmi- cro be driven with external clock in rc mode. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input volt- ages. 3: negative current is de?ed as current sourced by the pin.
pic16c63a/65b/73b/74b ds30605a-page 106 preliminary ? 1998 microchip technology inc. 14.4 a c (timing) characteristics 14.4.1 timing parameter symbology the timing parameter symbols have been created fol- lowing one of the following formats: 1. tpps2pps 3. t cc : st (i 2 c speci?ations only) 2. tpps 4. ts (i 2 c speci?ations only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s f fall p period h high r rise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c speci?ations only) cc hd hold su setup st dat data input hold sto stop condition sta start condition
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. preliminary ds30605a-page 107 14.4.2 timing conditions the temperature and voltages speci?d in table 14-1 apply to all timing speci?ations unless otherwise noted. figure 14-1 speci?s the load conditions for the timing speci?ations. table 14-1: temperature and voltage specifications - ac figure 14-1: load conditions for device timing specifications ac characteristics standard operating conditions (unless otherwise stated) operating temperature 0?c t a +70?c for commercial -40?c t a +85?c for industrial -40?c t a +125?c for extended operating voltage v dd range as described in dc spec section 14.1 and section 14.2. lc parts operate for commercial/industrial temps only. v dd /2 c l r l pin pin v ss v ss c l r l = 464 w c l = 50 pf for all pins except osc2/clkout but including d and e outputs as ports 15 pf for osc2 output load condition 1 load condition 2 note1: portd and porte are not imple- mented on the pic16c63a/73b.
pic16c63a/65b/73b/74b ds30605a-page 108 preliminary ? 1998 microchip technology inc. 14.4.3 timing diagrams and specifications figure 14-2: external clock timing table 14-2: external clock timing requirements param no. sym characteristic min typ? max units conditions 1a fosc external clkin frequency (note 1) dc 4 mhz rc and xt osc modes dc 4 mhz hs osc mode (-04) dc 20 mhz hs osc mode (-20) dc 200 khz lp osc mode oscillator frequency (note 1) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 4 20 mhz hs osc mode 5 200 khz lp osc mode 1 tosc external clkin period (note 1) 250 ns rc and xt osc modes 250 ns hs osc mode (-04) 50 ns hs osc mode (-20) 5 m s lp osc mode oscillator period (note 1) 250 ns rc osc mode 250 10,000 ns xt osc mode 250 250 ns hs osc mode (-04) 50 250 ns hs osc mode (-20) 5 m s lp osc mode 2t cy instruction cycle time (note 1) 200 dc ns t cy = 4/f osc 3* tosl, tosh external clock in (osc1) high or low time 100 ns xt oscillator 2.5 m s lp oscillator 15 ns hs oscillator 4* tosr, tosf external clock in (osc1) rise or fall time 25 ns xt oscillator 50 ns lp oscillator 15 ns hs oscillator * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all speci?d values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices. 3 3 4 4 1 2 q4 q1 q2 q3 q4 q1 osc1 clkout
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. preliminary ds30605a-page 109 figure 14-3: clkout and i/o timing table 14-3: clkout and i/o timing requirements param no. sym characteristic min typ? max units conditions 10* tosh2ckl osc1 - to clkout 75 200 ns note 1 11* tosh2ckh osc1 - to clkout - 75 200 ns note 1 12* tckr clkout rise time 35 100 ns note 1 13* tckf clkout fall time 35 100 ns note 1 14* tckl2iov clkout to port out valid 0.5t cy + 20 ns note 1 15* tiov2ckh port in valid before clkout - tosc + 200 ns note 1 16* tckh2ioi port in hold after clkout - 0 ns note 1 17* tosh2iov osc1 - (q1 cycle) to port out valid 50 150 ns 18* tosh2ioi osc1 - (q2 cycle) to port input invalid (i/o in hold time) standard 100 ns 18a* extended (lc) 200 ns 19* tiov2osh port input valid to osc1 - (i/o in setup time) 0 ns 20* tior port output rise time standard 10 40 ns 20a* extended (lc) 80 ns 21* tiof port output fall time standard 10 40 ns 21a* extended (lc) 80 ns 22??* tinp int pin high or low time t cy ns 23??* trbp rb7:rb4 change int high or low time t cy ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edge. note1: measurements are taken in rc mode where clkout output is 4 x t osc . note: refer to figure 14-1 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
pic16c63a/65b/73b/74b ds30605a-page 110 preliminary ? 1998 microchip technology inc. figure 14-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 14-5: brown-out reset timing table 14-4: reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset requirements parameter no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 2 m s v dd = 5v, -40?c to +125?c 31* twdt watchdog timer time-out period (no prescaler) 71833ms v dd = 5v, -40?c to +125?c 32 tost oscillation start-up timer period 1024 t osc t osc = osc1 period 33* tpwrt power-up timer period 28 72 132 ms v dd = 5v, -40?c to +125?c 34 t ioz i/o hi-impedance from mclr low or wdt reset 2.1 m s 35 t bor brown-out reset pulse width 100 m s v dd b vdd (d005) * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 14-1 for load conditions. v dd bv dd 35
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. preliminary ds30605a-page 111 figure 14-6: timer0 and timer1 external clock timings table 14-5: timer0 and timer1 external clock requirements param no. sym characteristic min typ? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 41* tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 42* tt0p t0cki period no prescaler t cy + 40 ns with prescaler greater of: 20 or t cy + 40 n ns n = prescale value (2, 4,..., 256) 45* tt1h t1cki high time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 standard 15 ns extended (lc) 25 ns asynchronous standard 30 ns extended (lc) 50 ns 46* tt1l t1cki low time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 standard 15 ns extended (lc) 25 ns asynchronous standard 30 ns extended (lc) 50 ns 47* tt1p t1cki input period synchronous standard greater of : 30 or t cy + 40 n ns n = prescale value (1, 2, 4, 8) extended (lc) greater of : 50 or t cy + 40 n n = prescale value (1, 2, 4, 8) asynchronous standard 60 ns extended (lc) 100 ns ft1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc ?200 khz 48 tckeztmr1 delay from external clock edge to timer increment 2tosc 7tosc * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 14-1 for load conditions. 46 47 45 48 41 42 40 t0cki t1oso/t1cki tmr0 or tmr1
pic16c63a/65b/73b/74b ds30605a-page 112 preliminary ? 1998 microchip technology inc. figure 14-7: capture/compare/pwm timings (ccp1 and ccp2) table 14-6: capture/compare/pwm requirements (ccp1 and ccp2) param no. sym characteristic min typ? max units conditions 50* tccl ccp1 and ccp2 input low time no prescaler 0.5t cy + 20 ns with prescaler standard 10 ns extended (lc) 20 ns 51* tcch ccp1 and ccp2 input high time no prescaler 0.5t cy + 20 ns with prescaler standard 10 ns extended (lc) 20 ns 52* tccp ccp1 and ccp2 input period 3t cy + 40 n ns n = prescale value (1,4, or 16) 53* tccr ccp1 and ccp2 output rise time standard 10 25 ns extended (lc) 25 45 ns 54* tccf ccp1 and ccp2 output fall time standard 10 25 ns extended (lc) 25 45 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 14-1 for load conditions. ccpx (capture mode) 50 51 52 ccpx 53 54 (compare or pwm mode)
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. preliminary ds30605a-page 113 figure 14-8: parallel slave port timing (pic16c65b/74b) table 14-7: parallel slave port requirements (pic16c65b/74b) parameter no. sym characteristic min typ? max units conditions 62* tdtv2wrh data in valid before wr - or cs - (setup time) 20 ns 63* twrh2dti wr - or cs - to data?n invalid (hold time) standard 20 ns extended (lc) 35 ns 64 trdl2dtv rd and cs to data?ut valid 80 ns 65* trdh2dti rd - or cs - to data?ut invalid 10 30 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 14-1 for load conditions. re2/cs re0/rd re1/wr rd7:rd0 62 63 64 65
pic16c63a/65b/73b/74b ds30605a-page 114 preliminary ? 1998 microchip technology inc. figure 14-9: example spi master mode timing (cke = 0) table 14-8: example spi mode requirements (master mode, cke = 0) param. no. symbol characteristic min typ? max units conditions 70 tssl2sch, tssl2scl ss to sck or sck - input t cy ns 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ns 71a single byte 40 ns note 1 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ns 72a single byte 40 ns note 1 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ns 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ns note 1 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ns 75 tdor sdo data output rise time standard 10 25 ns extended (lc) 20 45 ns 76 tdof sdo data output fall time 10 25 ns 78 tscr sck output rise time (master mode) standard 10 25 ns extended (lc) 20 45 ns 79 tscf sck output fall time (master mode) 10 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge standard 50 ns extended (lc) 100 ns ? data in ?yp column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note1: speci?ation 73a is only required if speci?ations 71a and 72a are used. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit6 - - - - - -1 msb in lsb in bit6 - - - -1 refer to figure 14-1 for load conditions.
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. preliminary ds30605a-page 115 figure 14-10: example spi master mode timing (cke = 1) table 14-9: example spi mode requirements (master mode, cke = 1) param. no. symbol characteristic min typ? max units conditions 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ns 71a single byte 40 ns note 1 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ns 72a single byte 40 ns note 1 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ns 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ns note 1 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ns 75 tdor sdo data output rise time standard 10 25 ns extended (lc) 20 45 ns 76 tdof sdo data output fall time 10 25 ns 78 tscr sck output rise time (master mode) standard 10 25 ns extended (lc) 20 45 ns 79 tscf sck output fall time (master mode) 10 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge standard 50 ns extended (lc) 100 ns 81 tdov2sch, tdov2scl sdo data output setup to sck edge t cy ns ? data in ?yp column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note1: speci?ation 73a is only required if speci?ations 71a and 72a are used. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit6 - - - - - -1 lsb in bit6 - - - -1 lsb refer to figure 14-1 for load conditions.
pic16c63a/65b/73b/74b ds30605a-page 116 preliminary ? 1998 microchip technology inc. figure 14-11: example spi slave mode timing (cke = 0) table 14-10: example spi mode requirements (slave mode timing (cke = 0) param. no. symbol characteristic min typ? max units conditions 70 tssl2sch, tssl2scl ss to sck or sck - input t cy ns 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ns 71a single byte 40 ns note 1 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ns 72a single byte 40 ns note 1 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ns 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ns note 1 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ns 75 tdor sdo data output rise time standard 10 25 ns extended (lc) 20 45 ns 76 tdof sdo data output fall time 10 25 ns 77 tssh2doz ss - to sdo output hi-impedance 10 50 ns 78 tscr sck output rise time (master mode) standard 10 25 ns extended (lc) 20 45 ns 79 tscf sck output fall time (master mode) 10 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge standard 50 ns extended (lc) 100 ns 83 tsch2ssh, tscl2ssh ss - after sck edge 1.5t cy + 40 ns ? data in ?yp column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note1: speci?ation 73a is only required if speci?ations 71a and 72a are used. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 sdi msb lsb bit6 - - - - - -1 msb in bit6 - - - -1 lsb in 83 refer to figure 14-1 for load conditions.
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. preliminary ds30605a-page 117 figure 14-12: example spi slave mode timing (cke = 1) table 14-11: example spi slave mode requirements (cke = 1) param. no. symbol characteristic min typ? max units conditions 70 tssl2sch, tssl2scl ss to sck or sck - input t cy ns 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ns 71a single byte 40 ns note 1 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ns 72a single byte 40 ns note 1 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ns note 1 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ns 75 tdor sdo data output rise time standard 10 25 ns extended (lc) 20 45 ns 76 tdof sdo data output fall time 10 25 ns 77 tssh2doz ss - to sdo output hi-impedance 10 50 ns 78 tscr sck output rise time (master mode) standard 10 25 ns extended (lc) 20 45 ns 79 tscf sck output fall time (master mode) 10 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge standard 50 ns extended (lc) 100 ns 82 tssl2dov sdo data output valid after ss edge standard 50 ns extended (lc) 100 ns 83 tsch2ssh, tscl2ssh ss - after sck edge 1.5t cy + 40 ns ? data in ?yp column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note1: speci?ation 73a is only required if speci?ations 71a and 72a are used. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 82 sdi 74 75, 76 msb bit6 - - - - - -1 lsb 77 msb in bit6 - - - -1 lsb in 80 83 refer to figure 14-1 for load conditions.
pic16c63a/65b/73b/74b ds30605a-page 118 preliminary ? 1998 microchip technology inc. figure 14-13: i 2 c bus start/stop bits timing table 14-12: i 2 c bus start/stop bits requirements parameter no. sym characteristic min typ max units conditions 90* t su : sta start condition 100 khz mode 4700 ns only relevant for repeated start condition setup time 400 khz mode 600 91* t hd : sta start condition 100 khz mode 4000 ns after this period the ?st clock pulse is generated hold time 400 khz mode 600 92* t su : sto stop condition 100 khz mode 4700 ns setup time 400 khz mode 600 93 t hd : sto stop condition 100 khz mode 4000 ns hold time 400 khz mode 600 * these parameters are characterized but not tested. note: refer to figure 14-1 for load conditions. 91 92 93 scl sda start condition stop condition 90
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. preliminary ds30605a-page 119 figure 14-14: i 2 c bus data timing table 14-13: i 2 c bus data requirements parameter no. sym characteristic min max units conditions 100* t high clock high time 100 khz mode 4.0 m s device must operate at a mini- mum of 1.5 mhz 400 khz mode 0.6 m s device must operate at a mini- mum of 10 mhz ssp module 1.5t cy 101* t low clock low time 100 khz mode 4.7 m s device must operate at a mini- mum of 1.5 mhz 400 khz mode 1.3 m s device must operate at a mini- mum of 10 mhz ssp module 1.5t cy 102* t r sda and scl rise time 100 khz mode 1000 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10-400 pf 103* t f sda and scl fall time 100 khz mode 300 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10-400 pf 90* t su : sta start condition setup time 100 khz mode 4.7 m s only relevant for repeated start condition 400 khz mode 0.6 m s 91* t hd : sta start condition hold time 100 khz mode 4.0 m s after this period the ?st clock pulse is generated 400 khz mode 0.6 m s 106* t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 m s 107* t su : dat data input setup time 100 khz mode 250 ns note 2 400 khz mode 100 ns 92* t su : sto stop condition setup time 100 khz mode 4.7 m s 400 khz mode 0.6 m s 109* t aa output valid from clock 100 khz mode 3500 ns note 1 400 khz mode ns 110* t buf bus free time 100 khz mode 4.7 m s time the bus must be free before a new transmission can start 400 khz mode 1.3 m s cb bus capacitive loading 400 pf * these parameters are characterized but not tested. note1: as a transmitter, the device must provide this internal minimum delay time to bridge the unde?ed region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode (400 khz) i 2 c-bus device can be used in a standard-mode (100 khz) i 2 c-bus system, but the requirement tsu:dat 3 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+tsu;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus speci?ation) before the scl line is released. note: refer to figure 14-1 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
pic16c63a/65b/73b/74b ds30605a-page 120 preliminary ? 1998 microchip technology inc. figure 14-15: usart synchronous transmission (master/slave) timing table 14-14: usart synchronous transmission requirements figure 14-16: usart synchronous receive (master/slave) timing table 14-15: usart synchronous receive requirements param no. sym characteristic min typ? max units conditions 120* tckh2dtv sync xmit (master & sla ve) clock high to data out valid standard 80 ns extended (lc) 100 ns 121* tckrf clock out rise time and fall time (master mode) standard 45 ns extended (lc) 50 ns 122* tdtrf data out rise time and fall time standard 45 ns extended (lc) 50 ns * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. parameter no. sym characteristic min typ? max units conditions 125* tdtv2ckl sync rcv (master & sla ve) data setup before ck (dt setup time) 15 ns 126* tckl2dtl data hold after ck (dt hold time) 15 ns * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 14-1 for load conditions. 121 121 120 122 rc6/tx/ck rc7/rx/dt pin pin note: refer to figure 14-1 for load conditions. 125 126 rc6/tx/ck rc7/rx/dt pin pin
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. preliminary ds30605a-page 121 table 14-16: a/d converter characteristics: pic16c73b/74b-04 (commercial, industrial, extended) pic16c73b/74b-20 (commercial, industrial, extended) pic16lc73b/74b-04 (commercial, industrial) param no. sym characteristic min typ? max units conditions a01 n r resolution 8-bits bit v ref = v dd = 5.12v, v ss v ain v ref a02 e abs total absolute error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a03 e il integral linearity error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a04 e dl differential linearity error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a05 e fs full scale error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a06 e off offset error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a10 monotonicity guaranteed v ss v ain v ref a20 v ref reference voltage 2.5v v dd + 0.3 v a25 v ain analog input voltage v ss - 0.3 v ref + 0.3 v a30 z ain recommended impedance of analog voltage source 10.0 k w a40 i ad a/d conversion current (v dd ) standard 180 m a average current consump- tion when a/d is on. (note 1) extended (lc) 90 m a a50 i ref v ref input current (note 2) 10 1000 10 m a m a during v ain acquisition. based on differential of v hold to v ain to charge c hold , see section 10.1. during a/d conversion cycle * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 2: v ref current is from ra3 pin or v dd pin, whichever is selected as reference input.
pic16c63a/65b/73b/74b ds30605a-page 122 preliminary ? 1998 microchip technology inc. figure 14-17: a/d conversion timing table 14-17: a/d conversion requirements param no. sym characteristic min typ? max units conditions 130 t ad a/d clock period standard 1.6 m st osc based, v ref 3 3.0v extended (lc) 2.0 m st osc based, v ref full range standard 2.0 4.0 6.0 m s a/d rc mode extended (lc) 3.0 6.0 9.0 m s a/d rc mode 131 t cnv conversion time (not including s/h time) (note 1) 11 11 t ad 132 t acq acquisition time note 2 5* 20 m s m s the minimum time is the ampli?r settling time. this may be used if the "new" input voltage has not changed by more than 1 lsb (i.e., 20.0 mv @ 5.12v) from the last sampled voltage (as stated on c hold ). 134 t go q4 to a/d clock start t osc /2 if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 135 t swc switching from convert ? sample time 1.5 t ad * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. this speci?ation ensured by design. note1: adres register may be read on the following t cy cycle. 2: see section 10.1 for min conditions. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (t osc /2) (1) 7 6 5432 10 note1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 tcy 134
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 123 15.0 dc and ac characteristics graphs and tables graphs and tables not available at this time.
pic16c63a/65b/73b/74b ds30605a-page 124 ? 1998 microchip technology inc. notes:
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 125 16.0 packaging information 16.1 p ac ka g e marking inf ormation 28-lead soic xxxxxxxxxxxxxxxxxxxx aabbcde mmmmmmmmmmmmmmmm example pic16c73b-20/so xxxxxxxxxxxxxxx aabbcde 28-lead pdip (skinny dip) mmmmmmmmmmmm example pic16c73b-04/sp example 28-lead cerdip windowed xxxxxxxxxxx xxxxxxxxxxx aabbcde pic16c73b/jw aabbcae xxxxxxxxxxxx xxxxxxxxxxxx 28-lead ssop 20i/ss025 pic16c73b example legend: xx...x microchip part number & customer speci? information* aa year code (last two digits of calendar year) bb week code (week of january 1 is week ?1? c facility code of the plant at which wafer is manufactured c = chandler, arizona, u.s.a., s = tempe, arizona, u.s.a. - 6 h = tempe, arizona, u.s.a. - 8 d mask revision number e assembly code of the plant or country of origin in which part was assembled note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer speci? information. * standard otp marking consists of microchip part number, year code, week code, facility code, mask rev# and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales of?e. for qtp devices, any special marking adders are included in qtp price. 9817hat 9817cat 9810/saa 9817sbp
pic16c63a/65b/73b/74b ds30605a-page 126 ? 1998 microchip technology inc. package marking information (contd) xxxxxxxxxxxxxxxxxx aabbcde 40-lead pdip mmmmmmmmmmmmmm example pic16c74b-04/p mmmmmmmmm xxxxxxxxxxx aabbcde 40-lead cerdip windowed xxxxxxxxxxx pic16c74b/jw example legend: xx...x microchip part number & customer speci? information* aa year code (last two digits of calendar year) bb week code (week of january 1 is week ?1? c facility code of the plant at which wafer is manufactured c = chandler, arizona, u.s.a., s = tempe, arizona, u.s.a. - 6 h = tempe, arizona, u.s.a. - 8 d mask revision number e assembly code of the plant or country of origin in which part was assembled note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer speci? information. * standard otp marking consists of microchip part number, year code, week code, facility code, mask rev# and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales of?e. for qtp devices, any special marking adders are included in qtp price. 9812saa 9805hat
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 127 package marking information (contd) 44-lead tqfp xxxxxxxxxx aabbcde mmmmmmmm xxxxxxxxxx example -20/pt pic16c74b 44-lead plcc mmmmmmmm aabbcde xxxxxxxxxx xxxxxxxxxx 44-lead mqfp xxxxxxxxxx aabbcde mmmmmmmm xxxxxxxxxx example pic16c74b -20/l example -20/pq pic16c74b legend: xx...x microchip part number & customer speci? information* aa year code (last two digits of calendar year) bb week code (week of january 1 is week ?1? c facility code of the plant at which wafer is manufactured c = chandler, arizona, u.s.a., s = tempe, arizona, u.s.a. - 6 h = tempe, arizona, u.s.a. - 8 d mask revision number e assembly code of the plant or country of origin in which part was assembled note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer speci? information. * standard otp marking consists of microchip part number, year code, week code, facility code, mask rev# and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales of?e. for qtp devices, any special marking adders are included in qtp price. 9804sat 9811hat 9803sat
pic16c63a/65b/73b/74b ds30605a-page 128 ? 1998 microchip technology inc. 16.2 k04-070 28-lead skinn y plastic dual in-line (sp) ?300 mil * controlling parameter. ? dimension ?1 does not include dam-bar protrusions. dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension ?1. dimensions ? and ? do not include mold ?sh or protrusions. mold ?sh or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions ? or ?. 0.320 0.270 0.280 1.345 0.125 0.015 0.070 0.140 0.008 0.000 0.040 0.016 mold draft angle bottom mold draft angle top overall row spacing radius to radius width molded package width tip to seating plane base to seating plane top of lead to seating plane top to seating plane upper lead width lower lead width pcb row spacing package length lead thickness shoulder radius number of pins dimension limits pitch units e b eb e1 a a1 a2 l d a c r n b1 ? b p min min 0.295 0.288 5 5 10 0.350 0.283 10 0.380 0.295 15 15 0.090 1.365 0.130 0.020 0.150 0.010 0.005 nom inches* 28 0.053 0.019 0.100 0.300 1.385 0.135 0.025 0.110 0.160 0.012 0.010 0.065 0.022 max 7.49 7.30 7.11 8.89 7.18 5 8.13 6.86 5 10 10 15 15 9.65 7.49 34.67 3.30 0.51 2.29 3.81 0.25 0.13 1.33 0.48 2.54 7.62 millimeters 1.78 34.16 3.18 0.38 3.56 0.20 0.00 1.02 0.41 nom 2.79 35.18 3.43 0.64 4.06 0.30 0.25 max 28 1.65 0.56 n 1 2 r d e c eb b e1 a p l a1 b b1 a a2
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 129 16.3 k04-080 28-lead ceramic dual in-line with windo w (jw) ?300 mil * controlling parameter. n 1 2 r overall row spacing radius to radius width package length tip to seating plane base to seating plane top of lead to seating plane top to seating plane shoulder radius upper lead width lower lead width pcb row spacing dimension limits window width window length package width lead thickness pitch number of pins units 0.170 a 0.130 w1 w2 0.290 d e1 eb e a2 l a1 1.430 0.345 0.255 0.285 0.135 0.015 0.107 b r c b1 n p 0.016 0.008 0.010 0.050 0.098 min millimeters 4.32 0.195 0.183 0.310 0.150 0.425 0.285 0.295 1.485 0.145 0.030 0.143 0.140 0.300 0.385 0.270 0.290 1.458 0.140 0.023 0.125 0.13 0.29 36.32 8.76 6.48 7.24 3.43 0.00 2.72 0.012 0.015 0.065 0.021 0.102 max nom 0.010 0.013 0.058 0.019 0.100 0.300 28 inches* 0.41 0.20 0.25 1.27 2.49 min 4.95 4.64 0.31 0.15 10.80 7.24 7.49 37.72 3.68 0.76 3.63 0.14 0.3 37.02 6.86 9.78 7.37 0.57 3.56 3.18 0.30 0.38 1.65 0.53 2.59 nom 28 0.47 0.32 0.25 1.46 2.54 7.62 max d w2 w1 e c e1 eb p a1 l b1 b a2 a
pic16c63a/65b/73b/74b ds30605a-page 130 ? 1998 microchip technology inc. 16.4 k04-052 28-lead plastic small outline (so) ? wide , 300 mil min p pitch mold draft angle bottom mold draft angle top lower lead width radius centerline gull wing radius shoulder radius chamfer distance outside dimension molded package width molded package length shoulder height overall pack. height lead thickness foot angle foot length standoff number of pins b a b ? c f x a2 a1 a n e1 l l1 r1 r2 e d dimension limits units 1.27 0.050 8 12 12 0.017 0 0.014 0 0.019 15 15 0.011 0.015 0.016 0.005 0.005 0.020 0.407 0.296 0.706 0.008 0.058 0.099 28 0.394 0.011 0.009 0.010 0 0.005 0.005 0.010 0.292 0.700 0.004 0.048 0.093 0.419 0.012 0.020 0.021 0.010 0.010 0.029 48 0.299 0.712 0.011 0.068 0.104 0.36 0 0 12 12 0.42 15 15 0.48 10.33 17.93 10.01 0.23 0.25 0.28 0.13 0.13 0.25 0 7.42 0.10 1.22 2.36 17.78 10.64 0.41 4 0.27 0.38 0.13 0.13 0.50 0.53 0.30 0.51 0.25 0.25 0.74 7.51 0.19 28 2.50 1.47 18.08 7.59 0.28 2.64 1.73 nom inches* max nom millimeters min max n 1 2 r1 r2 d p b e1 e l1 l c b 45 x f a1 a a a2 * controlling parameter. ? dimension ? does not include dam-bar protrusions. dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension ?. dimensions ? and ? do not include mold ?sh or protrusions. mold ?sh or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions ? or ?.
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 131 16.5 k04-073 28-lead plastic shrink small outline (ss) ?5.30 mm dimension limits mold draft angle bottom mold draft angle top lower lead width lead thickness radius centerline gull wing radius shoulder radius outside dimension molded package width molded package length shoulder height overall pack. height number of pins foot angle foot length standoff pitch b a b ? e l c l1 f r1 r2 e1 a2 d a1 a n p units max nom min max nom min 10 10 0.38 0.22 0.25 0.64 0.25 0.25 7.90 5.38 10.33 0.21 1.17 1.99 0.012 0 0.010 0 5 5 10 0.015 10 0.007 0.005 0.020 0.005 0.005 0.306 0.208 0.402 0.005 0.036 0.073 0.026 0.205 0.015 0.005 0.000 0 0.005 0.005 0.301 0.396 0.002 0.026 0.068 0.212 4 0.025 0.009 0.010 8 0.010 0.010 0.311 28 0.407 0.008 0.046 0.078 0.25 0 0 5 0.32 5 5.20 0.13 0.00 0.38 0.13 0.13 7.65 0 10.07 0.05 0.66 1.73 5.29 0.51 0.18 0.13 4 0.13 0.13 7.78 10.20 0.13 0.91 1.86 0.65 28 8 inches millimeters* n 1 2 r1 r2 d p b e e1 l l1 b c f a a1 a2 a * controlling parameter. ? dimension ? does not include dam-bar protrusions. dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension ?. dimensions ? and ? do not include mold ?sh or protrusions. mold ?sh or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions ? or ?.
pic16c63a/65b/73b/74b ds30605a-page 132 ? 1998 microchip technology inc. 16.6 k04-016 40-lead plastic dual in-line (p) ?600 mil * controlling parameter. ? dimension ?1 does not include dam-bar protrusions. dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension ?1. dimensions ? and ? do not include mold ?sh or protrusions. mold ?sh or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions ? or ?. n 2 1 r top to seating plane mold draft angle bottom mold draft angle top overall row spacing radius to radius width molded package width tip to seating plane base to seating plane top of lead to seating plane package length e1 b eb a l e d a2 a1 0.670 0.585 0.540 2.023 0.135 0.040 0.113 0.545 5 5 0.630 0.125 0.530 2.013 0.020 0.073 0.565 10 0.610 10 0.130 0.535 2.018 0.020 0.093 16.00 13.84 13.46 51.13 3.18 0.51 1.85 15 15 14.35 5 5 10 15.49 10 3.30 13.59 51.26 0.51 2.36 14.86 17.02 15 15 13.72 51.38 3.43 1.02 2.87 pcb row spacing lead thickness shoulder radius upper lead width lower lead width pitch number of pins dimension limits units p c a r b b1 ? n 0.160 0.011 0.010 0.055 0.020 nom inches* 0.110 0.009 0.000 0.045 0.016 min 0.100 0.160 0.010 0.005 0.050 0.018 40 0.600 max 2.79 0.23 0.00 1.14 0.41 min 2.54 4.06 0.25 0.13 1.27 0.46 nom millimeters 15.24 40 4.06 0.28 0.25 1.40 0.51 max a1 d e c b eb e1 a p l b b1 a a2
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 133 16.7 k04-014 40-lead ceramic dual in-line with windo w (jw) ?600 mil * controlling parameter. n 1 2 r window diameter overall row spacing radius to radius width package width package length tip to seating plane base to seating plane top of lead to seating plane top to seating plane lead thickness shoulder radius upper lead width lower lead width number of pins pcb row spacing dimension limits pitch e1 w eb d e l a2 a1 a c p b1 r b n 9.14 18.03 15.24 13.36 52.32 3.68 3.89 5.59 0.36 0.25 0.58 2.59 max 0.014 0.011 0.008 0.350 0.660 0.580 0.520 2.050 0.140 0.045 0.135 0.205 0.560 0.340 0.610 0.514 2.040 0.135 0.030 0.117 0.190 0.600 0.360 0.710 0.526 2.060 0.145 0.060 0.153 0.220 0.005 0.053 0.020 0.100 0.600 nom 0.000 0.050 0.016 0.098 min 40 0.102 0.010 0.055 0.023 max 0.28 0.20 14.22 15.49 8.64 13.06 51.82 3.43 0.00 2.97 4.83 14.73 16.76 8.89 13.21 52.07 3.56 1.14 3.43 5.21 min 2.49 1.27 0.00 0.41 2.54 1.33 0.13 0.50 15.24 nom 40 1.52 1.40 d w e c eb e1 p l a1 b1 b a a2 units inches* millimeters
pic16c63a/65b/73b/74b ds30605a-page 134 ? 1998 microchip technology inc. 16.8 k04-076 44-lead plastic thin quad flatpac k (pt) 10x10x1 mm bod y , 1.0/0.1 mm lead form 0.025 0.390 0.390 0.463 0.463 0.012 0.004 0.003 0.005 0.003 0.003 0.002 0.015 0.039 p mold draft angle bottom mold draft angle top pin 1 corner chamfer molded pack. width molded pack. length outside tip width outside tip length lower lead width lead thickness radius centerline gull wing radius shoulder radius shoulder height overall pack. height pins along width number of pins foot length foot angle standoff d b x a e l d1 e1 b ? c l1 f a1 r1 r2 a2 n1 a n dimension limits pitch units min 0.398 0.394 5 5 12 0.035 0.394 10 0.045 0.398 15 15 0.010 0 0.472 0.472 0.015 0.006 0.008 3.5 0.025 0.006 0.003 0.004 0.043 11 44 0.015 0.482 0.482 0.018 0.008 0.013 7 0.008 0.010 0.006 0.035 0.047 10.10 10.00 9.90 12 10 0.89 10.00 5 0.64 9.90 5 15 15 1.14 10.10 12.00 12.00 0.38 0.15 0.20 3.5 0.25 0.14 0.08 0.10 0.64 1.10 11 44 0.13 11.75 11.75 0.30 0.09 0.08 0 0.38 0.08 0.08 0.05 1.00 0.38 12.25 12.25 0.45 0.20 0.33 7 0.89 0.20 0.25 0.15 1.20 min nom inches 0.031 max 0.80 millimeters* nom max x x 45 n 1 2 r2 r1 l1 l b c f d1 d b p # leads = n1 e e1 a a1 a2 a * controlling parameter. ? dimension ? does not include dam-bar protrusions. dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension ?. dimensions ? and ? do not include mold ?sh or protrusions. mold ?sh or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions ? or ?. jedec equivalent: ms-026 acb
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 135 16.9 k04-071 44-lead plastic quad flatpac k (pq) 10x10x2 mm bod y , 1.6/0.15 mm lead form * controlling parameter. ? dimension ? does not include dam-bar protrusions. dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension ?. dimensions ? and ? do not include mold ?sh or protrusions. mold ?sh or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions ? or ?. jedec equivalent: ms-022 ab 0.025 0.390 0.390 0.510 0.510 0.012 0.005 0.011 0.015 0.005 0.005 0.002 0.032 0.079 p pitch mold draft angle bottom mold draft angle top pin 1 corner chamfer molded pack. width molded pack. length outside tip width outside tip length lower lead width radius centerline gull wing radius shoulder radius shoulder height overall pack. height pins along width lead thickness foot angle foot length standoff number of pins b a x e d c f a2 a1 a n1 n r2 e1 d1 b ? l1 l r1 dimension limits units min 0.80 0.031 0.635 12.95 12.95 0.035 0.394 0.394 5 5 10 12 15 15 0.045 0.398 0.398 0.012 0.520 0.520 0.015 0.007 0.016 0.020 0 3.5 0.005 0.006 0.044 0.086 11 44 0.015 0.009 0.530 0.530 0.018 0.021 0.025 7 0.010 0.010 0.056 0.093 5 5 9.90 9.90 10 12 10.00 10.00 0.89 1.143 10.10 10.10 15 15 0.30 0.13 0.13 0.30 0 0.28 0.38 0.18 13.20 13.20 0.37 3.5 0.41 0.51 0.13 0.05 0.81 2.00 0.13 0.15 1.11 11 2.18 44 0.38 13.45 13.45 0.45 0.23 0.53 0.64 7 0.25 0.25 1.41 2.35 min nom inches max millimeters* nom max x x 45 n 1 2 r2 r1 d d1 b p e1 e # leads = n1 l1 l c b f a a1 a a2
pic16c63a/65b/73b/74b ds30605a-page 136 ? 1998 microchip technology inc. 16.10 k04-048 44-lead plastic leaded chip carrier (l) ?square * controlling parameter. ? dimension ?1 does not include dam-bar protrusions. dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension ?1. dimensions ? and ? do not include mold ?sh or protrusions. mold ?sh or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions ? or ?. jedec equivalent: mo-047 ac 0.015 0.003 0.050 0.015 0.026 0.008 0.610 0.610 0.650 0.650 0.685 0.685 0.000 0.040 0.024 0.015 0.095 0.165 min p pitch mold draft angle bottom mold draft angle top j-bend inside radius shoulder inside radius upper lead length lower lead width upper lead width lead thickness pins along width footprint length footprint width molded pack. length molded pack. width overall pack. length overall pack. width corner chamfer (other) corner chamfer (1) side 1 chamfer dim. shoulder height overall pack. height standoff r2 r1 a b l b b1 ? d2 e2 ch2 ch1 a3 a2 e1 c n1 e d d1 a1 a number of pins dimension limits units n 1.27 0.050 0 0 0.005 0.025 5 5 0.058 0.018 0.029 0.035 0.010 0.065 0.021 0.032 10 10 0.690 0.620 0.010 0.620 11 0.653 0.653 0.690 0.005 0.045 0.029 0.023 0.103 0.173 0.695 0.012 0.630 0.630 0.656 0.656 0.695 0.010 0.050 0.034 0.030 0.110 0.180 0.64 0.13 1.46 0.46 0.74 0.08 0.38 0 0 1.27 0.38 0.66 5 5 0.25 0.89 10 10 1.65 0.53 0.81 0.25 15.75 15.75 16.59 16.59 17.53 17.53 0.13 1.14 0.74 0.57 2.60 4.38 17.40 15.49 0.20 15.49 16.51 16.51 17.40 0.00 1.02 0.61 0.38 2.41 4.19 17.65 11 16.00 0.30 16.00 16.66 16.66 17.65 0.25 1.27 0.86 0.76 2.79 4.57 inches* nom 44 max millimeters min nom max 44 1 ch2 x 45 n ch1 x 45 2 b r2 a1 r1 c e2 d1 d # leads = n1 e1 e a p l a3 a2 a 35 b1 b d2
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 137 appendix a: revision history appendix b: device differences the differences between the devices in this data sheet are listed in table b-1. appendix c: conversion considerations considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in table c-1. version date revision description a 7/98 this is a new data sheet. however, the devices described in this data sheet are the upgrades to the devices found in the pic16c6x data sheet , ds30234d, and the pic16c7x data sheet , ds30390e. table b-1: device differences difference pic16c63a pic16c65b pic16c73b pic16c74b a/d no no 5 channels, 8 bits 8 channels, 8 bits parallel slave port no yes no yes packages 28-pin pdip, 28-pin windowed cerdip, 28-pin soic, 28-pin ssop 40-pin pdip, 40-pin windowed cerdip, 44-pin tqfp, 44-pin mqfp, 44-pin plcc 28-pin pdip, 28-pin windowed cerdip, 28-pin soic, 28-pin ssop 40-pin pdip, 40-pin windowed cerdip, 44-pin tqfp, 44-pin mqfp, 44-pin plcc table c-1: conversion considerations difference pic16c63/65a/73a/74a pic16c63a/65b/73b/74b voltage range 2.5v - 6.0v 2.5v - 5.5v ssp module single mode spi 4-mode spi ssp module can only transmit one word in spi mode of enhanced ssp. n/a ccp module ccp does not reset tmr1 when in special event trigger mode. n/a usart module usart receiver errata in brgh=1 mode. n/a timer1 module writing to tmr1l register can cause over- ?w in tmr1h register. n/a
pic16c63a/65b/73b/74b ds30605a-page 138 ? 1998 microchip technology inc. appendix d: migration from baseline to midrange devices this section discusses how to migrate from a baseline device (i.e., pic16c5x) to a midrange device (i.e., pic16cxxx). the following are the list of modi?ations over the pic16c5x microcontroller family: 1. instruction word length is increased to 14-bits. this allows larger page sizes both in program memory (2k now as opposed to 512 before) and register ?e (128 bytes now versus 32 bytes before). 2. a pc high latch register (pclath) is added to handle program memory paging. bits pa2, pa1, pa0 are removed from status register. 3. data memory paging is rede?ed slightly. status register is modi?d. 4. four new instructions have been added: return, retfie, addlw , and sublw . two instructions tris and option are being phased out although they are kept for compati- bility with pic16c5x. 5. option and tris registers are made address- able. 6. interrupt capability is added. interrupt vector is at 0004h. 7. stack size is increased to 8 deep. 8. reset vector is changed to 0000h. 9. reset of all registers is revisited. five different reset (and wake-up) types are recognized. reg- isters are reset differently. 10. wake up from sleep through interrupt is added. 11. two separate timers, oscillator start-up timer (ost) and power-up timer (pwrt) are included for more reliable power-up. these tim- ers are invoked selectively to avoid unnecessary delays on power-up and wake-up. 12. portb has weak pull-ups and interrupt on change feature. 13. t0cki pin is also a port pin (ra4) now. 14. fsr is made a full eight bit register. 15. ?n-circuit serial programming is made possible. the user can program pic16cxx devices using only ?e pins: v dd , v ss , mclr /v pp , rb6 (clock) and rb7 (data in/out). 16. pcon status register is added with a power-on reset status bit (por ). 17. code protection scheme is enhanced such that portions of the program memory can be pro- tected, while the remainder is unprotected. 18. brown-out protection circuitry has been added. controlled by con?uration word bit boden. brown-out reset ensures the device is placed in a reset condition if v dd dips below a ?ed set- point. to convert code written for pic16c5x to pic16cxxx, the user should take the following steps: 1. remove any program memory page select operations (pa2, pa1, pa0 bits) for call , goto . 2. revisit any computed jump operations (write to pc or add to pc, etc.) to make sure page bits are set properly under the new scheme. 3. eliminate any data memory page switching. rede?e data variables to reallocate them. 4. verify all writes to status, option, and fsr registers since these have changed. 5. change reset vector to 0000h.
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 139 appendix e: bit/register cross- reference list adcs1:adcs0 ..................................adcon0<7:6> adie ...................................................pie1<6> adif ...................................................pir1<6> adon .................................................adcon0<0> bf ......................................................sspstat<0> bor ...................................................pcon<0> brgh .................................................txsta<2> c ........................................................status<0> ccp1ie ..............................................pie1<2> ccp1if ..............................................pir1<2> ccp1m3:ccp1m0 .............................ccp1con<3:0> ccp1x:ccp1y ..................................ccp1con<5:4> ccp2ie ..............................................pie2<0> ccp2if ..............................................pir2<0> ccp2m3:ccp2m0 .............................ccp2con<3:0> ccp2x:ccp2y ..................................ccp2con<5:4> chs2:chs0 .......................................adcon0<5:3> cke ....................................................sspstat<6> ckp ....................................................sspcon<4> cren .................................................rcsta<4> csrc .................................................txsta<7> d/a .....................................................sspstat<5> dc ......................................................status<1> ferr .................................................rcsta<2> gie .....................................................intcon<7> go/done ..........................................adcon0<2> ibf .....................................................trise<7> ibov ...................................................trise<5> inte ...................................................intcon<4> intedg .............................................option_reg<6> intf ...................................................intcon<1> irp .....................................................status<7> obf ....................................................trise<6> oerr .................................................rcsta<1> p .........................................................sspstat<4> pcfg2:pcfg0 ..................................adcon1<2:0> pd ......................................................status<3> peie ...................................................intcon<6> por ...................................................pcon<1> ps2:ps0 ............................................option_reg<2:0> psa ....................................................option_reg<3> pspie ................................................pie1<7> pspif .................................................pir1<7> pspmode .........................................trise<4> r/w ....................................................sspstat<2> rbie ...................................................intcon<3> rbif ...................................................intcon<0> rbpu .................................................option_reg<7> rcie ..................................................pie1<5> rcif ...................................................pir1<5> rp1:rp0 ............................................status<6:5> rx9 ....................................................rcsta<6> rx9d .................................................rcsta<0> s .........................................................sspstat<3> smp ...................................................sspstat<7> spen .................................................rcsta<7> sren .................................................rcsta<5> sspen ...............................................sspcon<5> sspie ................................................pie1<3> sspif .................................................pir1<3> sspm3:sspm0 ..................................sspcon<3:0> sspov ...............................................sspcon<6> sync .................................................txsta<4> t0cs ..................................................option_reg<5> t0ie ................................................... intcon<5> t0if ................................................... intcon<2> t0se .................................................. option_reg<4> t1ckps1:t1ckps0 .......................... t1con<5:4> t1oscen .......................................... t1con<3> t1sync ............................................ t1con<2> t2ckps1:t2ckps0 .......................... t2con<1:0> tmr1cs ............................................ t1con<1> tmr1ie ............................................. pie1<0> tmr1if .............................................. pir1<0> tmr1on ........................................... t1con<0> tmr2ie ............................................. pie1<1> tmr2if .............................................. pir1<1> tmr2on ........................................... t2con<2> t o ...................................................... status<4> toutps3:toutps0 ......................... t2con<6:3> trmt ................................................. txsta<1> tx9 .................................................... txsta<6> tx9d ................................................. txsta<0> txen ................................................. txsta<5> txie ................................................... pie1<4> txif ................................................... pir1<4> ua ...................................................... sspstat<1> wcol ................................................ sspcon<7> z ........................................................ status<2>
pic16c63a/65b/73b/74b ds30605a-page 140 ? 1998 microchip technology inc. notes:
1998 microchip technology inc. ds30605a-page 141 pic16c63a/65b/73b/74b index a a/d ...................................................................................... 75 a/d converter enable (adie bit) ................................ 18 a/d converter flag (adif bit) .............................. 19, 77 a/d converter interrupt, configuring .......................... 77 adcon0 register................................................. 13, 75 adcon1 register........................................... 14, 75, 76 adres register ............................................. 13, 75, 77 analog port pins ....................................... 7, 8, 9, 34, 35 analog port pins, configuring..................................... 79 block diagram............................................................. 77 block diagram, analog input model............................ 78 channel select (chs2:chs0 bits) ............................. 75 clock select (adcs1:adcs0 bits)............................. 75 configuring the module............................................... 77 conversion clock (t ad ) .............................................. 79 conversion status (go/done bit) ....................... 75, 77 conversions ................................................................ 80 converter characteristics ......................................... 121 module on/off (adon bit).......................................... 75 port configuration control (pcfg2:pcfg0 bits) ....... 76 sampling requirements.............................................. 78 special event trigger (ccp)................................. 47, 80 timing diagram......................................................... 122 absolute maximum ratings .............................................. 101 adcon0 register......................................................... 13, 75 adcs1:adcs0 bits .................................................... 75 adon bit .................................................................... 75 chs2:chs0 bits......................................................... 75 go/done bit........................................................ 75, 77 adcon1 register................................................... 14, 75, 76 pcfg2:pcfg0 bits .................................................... 76 adres register ..................................................... 13, 75, 77 architecture pic16c63a/pic16c73b block diagram....................... 5 pic16c65b/pic16c74b block diagram....................... 6 assembler mpasm assembler..................................................... 98 b banking, data memory ................................................. 11, 15 brown-out reset (bor) .............................. 81, 83, 85, 86, 87 bor enable (boden bit)........................................... 81 bor status (bor bit)................................................. 22 timing diagram......................................................... 110 c capture (ccp module) ....................................................... 46 block diagram............................................................. 46 ccp pin configuration................................................ 46 ccpr1h:ccpr1l registers...................................... 46 changing between capture prescalers...................... 46 software interrupt ....................................................... 46 timer1 mode selection ............................................... 46 capture/compare/pwm (ccp)........................................... 45 ccp1 .......................................................................... 45 ccp1con register ...................................... 13, 45 ccpr1h register......................................... 13, 45 ccpr1l register ......................................... 13, 45 enable (ccp1ie bit) ........................................... 18 flag (ccp1if bit) ............................................... 19 rc2/ccp1 pin.................................................. 7, 9 ccp2 .......................................................................... 45 ccp2con register ...................................... 13, 45 ccpr2h register......................................... 13, 45 ccpr2l register ......................................... 13, 45 enable (ccp2ie bit) ........................................... 20 flag (ccp2if bit) ............................................... 21 rc1/t1osi/ccp2 pin ...................................... 7, 9 interaction of two ccp modules................................ 45 timer resources ........................................................ 45 timing diagram ........................................................ 112 ccp1con register............................................................ 45 ccp1m3:ccp1m0 bits .............................................. 45 ccp1x:ccp1y bits.................................................... 45 ccp2con register............................................................ 45 ccp2m3:ccp2m0 bits .............................................. 45 ccp2x:ccp2y bits.................................................... 45 code protection ............................................................ 81, 94 cp1:cp0 bits.............................................................. 81 compare (ccp module) ..................................................... 47 block diagram ............................................................ 47 ccp pin configuration ............................................... 47 ccpr1h:ccpr1l registers ..................................... 47 software interrupt ....................................................... 47 special event trigger ..................................... 41, 47, 80 timer1 mode selection............................................... 47 configuration bits ............................................................... 81 conversion considerations .............................................. 137 d data memory ...................................................................... 11 bank select (rp1:rp0 bits) ................................. 11, 15 general purpose registers ........................................ 11 register file map ....................................................... 12 special function registers................................... 12, 13 dc characteristics.................................................... 102, 104 development support ......................................................... 97 development tools............................................................. 97 device differences ........................................................... 137 direct addressing ............................................................... 24 e electrical characteristics .................................................. 101 errata .....................................................................................4 external power-on reset circuit ........................................ 85 f firmware instructions ......................................................... 95 ftp site ............................................................................... 147 fuzzy logic dev. system ( fuzzy tech -mp) .................... 99 i i/o ports ............................................................................. 25 i 2 c (ssp module) ............................................................... 56 ack pulse .......................................... 56, 57, 58, 59, 60 addressing.................................................................. 57 block diagram ............................................................ 56 buffer full status (bf bit)........................................... 52 clock polarity select (ckp bit)................................... 53 data/address (d/a bit) ............................................... 52 master mode............................................................... 60 mode select (sspm3:sspm0 bits)............................ 53 multi-master mode...................................................... 60 read/write bit information (r/w bit)........ 52, 57, 58, 59 receive overflow indicator (sspov bit).................... 53 reception ................................................................... 58 reception timing diagram ......................................... 58 serial clock (rc3/sck/scl) ..................................... 59 slave mode................................................................. 56 start (s bit) ........................................................... 52, 60 stop (p bit) ........................................................... 52, 60 synchronous serial port enable (sspen bit)............ 53 timing diagram, data............................................... 119 timing diagram, start/stop bits ............................... 118 transmission .............................................................. 59 update address (ua bit) ............................................ 52 icepic low-cost pic16cxxx in-circuit emulator ............ 97
pic16c63a/65b/73b/74b ds30605a-page 142 1998 microchip technology inc. id locations .................................................................. 81, 94 in-circuit serial programming (icsp) ........................... 81, 94 indirect addressing ............................................................. 24 fsr register .................................................. 11, 13, 24 indf register ............................................................. 13 instruction format ............................................................... 95 instruction set ..................................................................... 95 summary table........................................................... 96 intcon register .......................................................... 13, 17 gie bit......................................................................... 17 inte bit....................................................................... 17 intf bit ....................................................................... 17 peie bit....................................................................... 17 rbie bit ...................................................................... 17 rbif bit................................................................. 17, 27 t0ie bit ....................................................................... 17 t0if bit ....................................................................... 17 interrupt sources........................................................... 81, 90 a/d conversion complete .......................................... 77 block diagram............................................................. 90 capture complete (ccp)............................................ 46 compare complete (ccp).......................................... 47 interrupt on change (rb7:rb4 )................................. 27 rb0/int pin, external......................................... 7, 8, 91 ssp receive/transmit complete ............................... 51 tmr0 overflow ..................................................... 38, 91 tmr1 overflow ..................................................... 39, 41 tmr2 to pr2 match ................................................... 44 tmr2 to pr2 match (pwm) ................................. 43, 48 usart receive/transmit complete .......................... 61 interrupts, context saving during ....................................... 91 interrupts, enable bits a/d converter enable (adie bit) ................................ 18 ccp1 enable (ccp1ie bit)................................... 18, 46 ccp2 enable (ccp2ie bit)......................................... 20 global interrupt enable (gie bit) .......................... 17, 90 interrupt on change (rb7:rb4) enable (rbie bit) .............................................................. 17, 91 peripheral interrupt enable (peie bit) ........................ 17 psp read/write enable (pspie bit) .......................... 18 rb0/int enable (inte bit) ......................................... 17 ssp enable (sspie bit) ............................................. 18 tmr0 overflow enable (t0ie bit)............................... 17 tmr1 overflow enable (tmr1ie bit) ......................... 18 tmr2 to pr2 match enable (tmr2ie bit) ................. 18 usart receive enable (rcie bit) ............................ 18 usart transmit enable (txie bit) ............................ 18 interrupts, flag bits a/d converter flag (adif bit) .............................. 19, 77 ccp1 flag (ccp1if bit) ................................. 19, 46, 47 ccp2 flag (ccp2if bit) ............................................. 21 interrupt on change (rb7:rb4) flag (rbif bit) ........................................................ 17, 27, 91 psp read/write flag (pspif bit)............................... 19 rb0/int flag (intf bit).............................................. 17 ssp flag (sspif bit).................................................. 19 tmr0 overflow flag (t0if bit) ............................. 17, 91 tmr1 overflow flag (tmr1if bit) ............................. 19 tmr2 to pr2 match flag (tmr2if bit) ...................... 19 usart receive flag (rcif bit) ................................. 19 usart transmit flag (txie bit) ................................ 19 k keeloq evaluation and programming tools.................... 99 m master clear (mclr ) ........................................................ 7, 8 mclr reset, normal operation ..................... 83, 86, 87 mclr reset, sleep...................................... 83, 86, 87 memory organization data memory .............................................................. 11 program memory ........................................................ 11 mp-driveway - application code generator .................. 99 mplab c ............................................................................ 99 mplab integrated development environment software ..................................................................... 98 o on-line support ............................................................... 147 opcode field descriptions............................................... 95 option_reg register................................................ 14, 16 intedg bit ................................................................. 16 ps2:ps0 bits ........................................................ 16, 37 psa bit ................................................................. 16, 37 rbpu bit .................................................................... 16 t0cs bit ............................................................... 16, 37 t0se bit ............................................................... 16, 37 osc1/clkin pin .............................................................. 7, 8 osc2/clkout pin .......................................................... 7, 8 oscillator configuration ................................................ 81, 82 hs......................................................................... 82, 86 lp ......................................................................... 82, 86 rc .................................................................. 82, 83, 86 selection (fosc1:fosc0 bits) ................................. 81 xt ......................................................................... 82, 86 oscillator, timer1.......................................................... 39, 41 oscillator, wdt................................................................... 92 p packaging ......................................................................... 125 paging, program memory............................................. 11, 23 parallel slave port (psp).......................................... 9, 31, 35 block diagram ............................................................ 35 re0/rd /an5 pin .............................................. 9, 34, 35 re1/wr /an6 pin ............................................. 9, 34, 35 re2/cs /an7 pin .............................................. 9, 34, 35 read waveforms ........................................................ 36 read/write enable (pspie bit) .................................. 18 read/write flag (pspif bit)....................................... 19 select (pspmode bit) ................................... 31, 33, 35 timing diagram ........................................................ 113 write waveforms ........................................................ 35 pcon register ............................................................. 22, 86 bor bit....................................................................... 22 por bit....................................................................... 22 picdem-1 low-cost picmicro demo board ..................... 98 picdem-2 low-cost pic16cxx demo board................... 98 picdem-3 low-cost pic16cxxx demo board ................ 98 picmaster in-circuit emulator ..................................... 97 picstart plus entry level development system ......... 97 pie1 register................................................................ 14, 18 adie bit ...................................................................... 18 ccp1ie bit ................................................................. 18 pspie bit .................................................................... 18 rcie bit ...................................................................... 18 sspie bit .................................................................... 18 tmr1ie bit ................................................................. 18 tmr2ie bit ................................................................. 18 txie bit ...................................................................... 18 pie2 register................................................................ 14, 20 ccp2ie bit ................................................................. 20 pinout descriptions pic16c63a/pic16c73b............................................... 7 pic16c65b/pic16c74b............................................... 8 pir1 register ............................................................... 13, 19 adif bit ...................................................................... 19 ccp1if bit.................................................................. 19 pspif bit .................................................................... 19
1998 microchip technology inc. ds30605a-page 143 pic16c63a/65b/73b/74b rcif bit ...................................................................... 19 sspif bit .................................................................... 19 tmr1if bit.................................................................. 19 tmr2if bit.................................................................. 19 txif bit ....................................................................... 19 pir2 register................................................................ 13, 21 ccp2if bit .................................................................. 21 pointer, fsr ....................................................................... 24 porta.............................................................................. 7, 8 analog port pins ....................................................... 7, 8 initialization ................................................................. 25 porta register ................................................... 13, 25 ra3:ra0 and ra5 port pins ...................................... 25 ra4/t0cki pin.................................................... 7, 8, 25 ra5/ss /an4 pin ................................................. 7, 8, 54 trisa register ..................................................... 14, 25 portb.............................................................................. 7, 8 initialization ................................................................. 27 portb register ................................................... 13, 27 pull-up enable (rbpu bit) .......................................... 16 rb0/int edge select (intedg bit)............................ 16 rb0/int pin, external......................................... 7, 8, 91 rb3:rb0 port pins ..................................................... 27 rb7:rb4 interrupt on change .................................... 91 rb7:rb4 interrupt on change enable (rbie bit) .............................................................. 17, 91 rb7:rb4 interrupt on change flag (rbif bit) ........................................................ 17, 27, 91 rb7:rb4 port pins ..................................................... 27 trisb register ..................................................... 14, 27 portc ............................................................................. 7, 9 block diagram............................................................. 29 initialization ................................................................. 29 portc register ................................................... 13, 29 rc0/t1oso/t1cki pin ............................................ 7, 9 rc1/t1osi/ccp2 pin............................................... 7, 9 rc2/ccp1 pin .......................................................... 7, 9 rc3/sck/scl pin ........................................ 7, 9, 54, 59 rc4/sdi/sda pin ............................................... 7, 9, 54 rc5/sdo pin...................................................... 7, 9, 54 rc6/tx/ck pin ................................................... 7, 9, 62 rc7/rx/dt pin............................................. 7, 9, 62, 63 trisc register............................................... 14, 29, 61 portd ........................................................................... 9, 35 block diagram............................................................. 31 parallel slave port (psp) function ............................. 31 portd register ................................................... 13, 31 trisd register..................................................... 14, 31 porte.................................................................................. 9 analog port pins ............................................... 9, 34, 35 block diagram............................................................. 33 input buffer full status (ibf bit) ................................. 33 input buffer overflow (ibov bit) ................................. 33 output buffer full status (obf bit)............................. 33 porte register ................................................... 13, 33 psp mode select (pspmode bit) ................. 31, 33, 35 re0/rd /an5 pin............................................... 9, 34, 35 re1/wr /an6 pin.............................................. 9, 34, 35 re2/cs /an7 pin............................................... 9, 34, 35 trise register ..................................................... 14, 33 postscaler, timer2 select (toutps3:toutps0 bits) ............................. 43 postscaler, wdt ................................................................. 37 assignment (psa bit) ........................................... 16, 37 block diagram............................................................. 38 rate select (ps2:ps0 bits) .................................. 16, 37 switching between timer0 and wdt ......................... 38 power-on reset (por)............................... 81, 83, 85, 86, 87 oscillator start-up timer (ost)............................ 81, 85 por status (por bit) ................................................ 22 power control (pcon) register................................. 86 power-down (pd bit) ............................................ 15, 83 power-on reset circuit, external ............................... 85 power-up timer (pwrt) ...................................... 81, 85 pwrt enable (pwrte bit) ....................................... 81 time-out (to bit).................................................. 15, 83 time-out sequence .................................................... 86 time-out sequence on power-up......................... 88, 89 timing diagram ........................................................ 110 prescaler, capture.............................................................. 46 prescaler, timer0 ............................................................... 37 assignment (psa bit) ........................................... 16, 37 block diagram ............................................................ 38 rate select (ps2:ps0 bits) .................................. 16, 37 switching between timer0 and wdt......................... 38 prescaler, timer1 ............................................................... 40 select (t1ckps1:t1ckps0 bits) .............................. 39 prescaler, timer2 ............................................................... 48 select (t2ckps1:t2ckps0 bits) .............................. 43 pro mate ii universal programmer .............................. 97 product identification system ........................................... 149 program counter pcl register ........................................................ 13, 23 pclath register ........................................... 13, 23, 91 reset conditions ........................................................ 86 program memory ................................................................ 11 interrupt vector........................................................... 11 paging .................................................................. 11, 23 program memory map................................................ 11 reset vector............................................................... 11 program verification ........................................................... 94 programming pin (v pp ) .................................................... 7, 8 programming, device instructions...................................... 95 pwm (ccp module) ........................................................... 48 block diagram ............................................................ 48 ccpr1h:ccpr1l registers ..................................... 48 duty cycle .................................................................. 48 example frequencies/resolutions ............................. 49 output diagram .......................................................... 48 period ......................................................................... 48 set-up for pwm operation......................................... 49 tmr2 to pr2 match ............................................. 43, 48 tmr2 to pr2 match enable (tmr2ie bit) ................. 18 tmr2 to pr2 match flag (tmr2if bit) ..................... 19 q q-clock............................................................................... 48 r rcsta register ................................................................. 62 cren bit .................................................................... 62 ferr bit..................................................................... 62 oerr bit .................................................................... 62 rx9 bit ....................................................................... 62 rx9d bit..................................................................... 62 spen bit............................................................... 61, 62 sren bit .................................................................... 62 reader response............................................................. 148 register file ....................................................................... 11 register file map ............................................................... 12 reset ............................................................................ 81, 83 block diagram ............................................................ 84 reset conditions for all registers.............................. 87 reset conditions for pcon register ......................... 86 reset conditions for program counter ...................... 86 reset conditions for status register ..................... 86
pic16c63a/65b/73b/74b ds30605a-page 144 1998 microchip technology inc. timing diagram......................................................... 110 revision history ................................................................ 137 s seeval evaluation and programming system ............... 99 sleep..................................................................... 81, 83, 93 software simulator (mplab-sim)....................................... 99 special features of the cpu............................................... 81 special function registers ........................................... 12, 13 speed, operating .......................................................... 1, 101 spi (ssp module) block diagram............................................................. 54 buffer full status (bf bit) ........................................... 52 clock edge select (cke bit)....................................... 52 clock polarity select (ckp bit) ................................... 53 data input sample phase (smp bit)........................... 52 mode select (sspm3:sspm0 bits) ............................ 53 receive overflow indicator (sspov bit) .................... 53 serial clock (rc3/sck/scl)...................................... 54 serial data in (rc4/sdi/sda) .................................... 54 serial data out (rc5/sdo) ........................................ 54 slave select (ra5/ss /an4)........................................ 54 synchronous serial port enable (sspen bit) ............ 53 ssp ..................................................................................... 51 enable (sspie bit)...................................................... 18 flag (sspif bit) .......................................................... 19 ra5/ss /an4 pin ....................................................... 7, 8 rc3/sck/scl pin .................................................... 7, 9 rc4/sdi/sda pin ..................................................... 7, 9 rc5/sdo pin............................................................ 7, 9 rcsta register ......................................................... 13 spbrg register ......................................................... 14 sspadd register....................................................... 14 sspbuf register ....................................................... 13 sspcon register ................................................ 13, 53 sspstat register ............................................... 14, 52 tmr2 output for clock shift ................................. 43, 44 txsta register .......................................................... 14 write collision detect (wcol bit) .............................. 53 sspcon register............................................................... 53 ckp bit ....................................................................... 53 sspen bit................................................................... 53 sspm3:sspm0 bits.................................................... 53 sspov bit .................................................................. 53 wcol bit .................................................................... 53 sspstat register ............................................................. 52 bf bit .......................................................................... 52 cke bit ....................................................................... 52 d/a bit......................................................................... 52 p bit....................................................................... 52, 60 r/w bit ...................................................... 52, 57, 58, 59 s bit ...................................................................... 52, 60 smp bit ....................................................................... 52 ua bit.......................................................................... 52 stack ................................................................................... 23 status register.................................................... 13, 15, 91 c bit ............................................................................ 15 dc bit.......................................................................... 15 irp bit......................................................................... 15 pd bit.................................................................... 15, 83 rp1:rp0 bits .............................................................. 15 to bit .................................................................... 15, 83 z bit............................................................................. 15 t t1con register............................................................ 13, 39 t1ckps1:t1ckps0 bits ............................................ 39 t1oscen bit.............................................................. 39 t1sync bit................................................................. 39 tmr1cs bit................................................................ 39 tmr1on bit ............................................................... 39 t2con register ........................................................... 13, 43 t2ckps1:t2ckps0 bits............................................ 43 tmr2on bit ............................................................... 43 toutps3:toutps0 bits .......................................... 43 timer0................................................................................. 37 block diagram ............................................................ 37 clock source edge select (t0se bit) .................. 16, 37 clock source select (t0cs bit) ........................... 16, 37 overflow enable (t0ie bit) ......................................... 17 overflow flag (t0if bit) ....................................... 17, 91 overflow interrupt ................................................. 38, 91 ra4/t0cki pin, external clock ................................ 7, 8 timing diagram ........................................................ 111 tmr0 register ........................................................... 13 timer1................................................................................. 39 block diagram ............................................................ 40 capacitor selection .................................................... 41 clock source select (tmr1cs bit) ............................ 39 external clock input sync (t1sync bit).................... 39 module on/off (tmr1on bit) .................................... 39 oscillator............................................................... 39, 41 oscillator enable (t1oscen bit) ............................... 39 overflow enable (tmr1ie bit) ................................... 18 overflow flag (tmr1if bit) ........................................ 19 overflow interrupt ................................................. 39, 41 rc0/t1oso/t1cki pin ............................................ 7, 9 rc1/t1osi/ccp2 pin .............................................. 7, 9 special event trigger (ccp) ................................ 41, 47 t1con register ................................................... 13, 39 timing diagram ........................................................ 111 tmr1h register ................................................... 13, 39 tmr1l register ................................................... 13, 39 timer2 block diagram ............................................................ 44 pr2 register .................................................. 14, 43, 48 ssp clock shift .................................................... 43, 44 t2con register ................................................... 13, 43 tmr2 register ..................................................... 13, 43 tmr2 to pr2 match enable (tmr2ie bit) ................. 18 tmr2 to pr2 match flag (tmr2if bit) ..................... 19 tmr2 to pr2 match interrupt......................... 43, 44, 48 timing diagrams i 2 c reception (7-bit address)..................................... 58 time-out sequence on power-up ......................... 88, 89 usart asynchronous master transmission ............. 67 usart asynchronous reception .............................. 68 usart synchronous reception ................................ 72 usart synchronous transmission ........................... 71 wake-up from sleep via interrupt ............................ 94 timing diagrams and specifications ................................ 108 a/d conversion ........................................................ 122 brown-out reset (bor)............................................ 110 capture/compare/pwm (ccp) ................................ 112 clkout and i/o ...................................................... 109 external clock .......................................................... 108 i 2 c bus data............................................................. 119 i 2 c bus start/stop bits ............................................. 118 oscillator start-up timer (ost) ................................ 110 parallel slave port (psp) ......................................... 113 power-up timer (pwrt) .......................................... 110 reset ........................................................................ 110 timer0 and timer1 ................................................... 111 usart synchronous receive ( master/slave) ......................................................... 120 usart synchronoustransmission
1998 microchip technology inc. ds30605a-page 145 pic16c63a/65b/73b/74b ( master/slave).......................................................... 120 watchdog timer (wdt) ............................................ 110 trise register ............................................................. 14, 33 ibf bit ......................................................................... 33 ibov bit ...................................................................... 33 obf bit ....................................................................... 33 pspmode bit................................................. 31, 33, 35 txsta register .................................................................. 61 brgh bit .............................................................. 61, 63 csrc bit..................................................................... 61 sync bit..................................................................... 61 trmt bit..................................................................... 61 tx9 bit ........................................................................ 61 tx9d bit...................................................................... 61 txen bit ..................................................................... 61 u usart ................................................................................ 61 asynchronous mode ................................................... 66 master transmission .......................................... 67 receive block diagram ...................................... 68 reception............................................................ 68 transmit block diagram ..................................... 66 baud rate generator (brg)....................................... 63 baud rate error, calculating .............................. 63 baud rate formula............................................. 63 baud rates, asynchronous mode (brgh=0) ........................................................... 64 baud rates, asynchronous mode (brgh=1) ........................................................... 65 baud rates, synchronous mode ........................ 64 high baud rate select (brgh bit) .............. 61, 63 sampling............................................................. 63 clock source select (csrc bit)................................. 61 continuous receive enable (cren bit)..................... 62 framing error (ferr bit) ........................................... 62 mode select (sync bit) ............................................. 61 overrun error (oerr bit) ........................................... 62 rc6/tx/ck pin ......................................................... 7, 9 rc7/rx/dt pin......................................................... 7, 9 rcreg register......................................................... 13 rcsta register ......................................................... 62 receive data, 9th bit (rx9d bit) ................................ 62 receive enable (rcie bit).......................................... 18 receive enable, 9-bit (rx9 bit) .................................. 62 receive flag (rcif bit) .............................................. 19 serial port enable (spen bit)............................... 61, 62 single receive enable (sren bit) ............................. 62 synchronous master mode ......................................... 70 reception............................................................ 72 timing diagram, synchronous receive ........... 120 timing diagram, synchronous transmission .................................................... 120 transmission ...................................................... 71 synchronous slave mode ........................................... 73 transmit data, 9th bit (tx9d)..................................... 61 transmit enable (txen bit)........................................ 61 transmit enable (txie bit) ......................................... 18 transmit enable, nine-bit (tx9 bit) ............................ 61 transmit flag (txie bit) ............................................. 19 transmit shift register status (trmt bit).................. 61 txreg register ......................................................... 13 txsta register .......................................................... 61 w w register .......................................................................... 91 wake-up from sleep................................................... 81, 93 interrupts............................................................... 86, 87 mclr reset ............................................................... 87 timing diagram .......................................................... 94 wdt reset ................................................................. 87 watchdog timer (wdt)................................................ 81, 92 block diagram ............................................................ 92 enable (wdte bit) ............................................... 81, 92 programming considerations ..................................... 92 rc oscillator .............................................................. 92 time-out period .......................................................... 92 timing diagram ........................................................ 110 wdt reset, normal operation....................... 83, 86, 87 wdt reset, sleep ....................................... 83, 86, 87 www, on-line support ............................................... 4, 147
pic16c63a/65b/73b/74b ds30605a-page 146 1998 microchip technology inc. notes:
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 147 systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-602-786-7302 for the rest of the world. trademarks: the microchip name, logo, pic, picstart, picmaster and pro mate are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. picmicro, flex rom, mplab and fuzzy lab are trademarks and sqtp is a service mark of microchip in the u.s.a. all other trademarks mentioned herein are the property of their respective companies. on-line support microchip provides on-line support on the microchip world wide web (www) site. the web site is used by microchip as a means to make ?es and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the ?e transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.futureone.com/pub/microchip the web site and ?e transfer site provide a variety of services. users may download ?es for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip speci? business information is also available, including listings of microchip sales of?es, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development sys- tems, technical information and more listing of seminars and events 980106
pic16c63a/65b/73b/74b ds30605a-page 148 1998 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (602) 786-7578. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you ?d the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds30605a pic16c63a/65b/73b/74b
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 149 pic16c63a/65b/73b/74b product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales of?e. * jw devices are uv erasable and can be programmed to any device con?uration. jw devices meet the electrical requirement of each oscillator type (including lc devices). p ar t no . -xx x /xx xxx pattern package temperature range frequency range device device pic16c6x (1) , pic16c6xt (2) ;v dd range 4.0v to 5.5v pic16lc6x (1) , pic16lc6xt (2) ;v dd range 2.5v to 5.5v pic16c7x (1) , pic16c7xt (2) ;v dd range 4.0v to 5.5v pic16lc7x (1) , pic16lc7xt (2) ;v dd range 2.5v to 5.5v frequency range 04 = 4 mhz 20 = 20 mhz temperature range blank = 0 c to 70 c (commercial) i = -40 c to +85 c (industrial) e = -40 c to +125 c (extended) package jw = windowed cerdip pq = mqfp (metric pqfp) pt = tqfp (thin quad flatpack) so = soic sp = skinny plastic dip p = pdip l = plcc ss = ssop pattern qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic16c74b -04/p 301 = commercial temp., pdip package, 4 mhz, normal v dd limits, qtp pattern #301. b) pic16lc63a - 04i/so = industrial temp., soic package, 200 khz, extended v dd limits. c) pic16c65b - 20i/p = industrial temp., pdip package, 20mhz, normal v dd limits. note 1: c = cmos lc = low power cmos 2: t = in tape and reel - soic, ssop, plcc, qfp, tq and fp packages only.
pic16c63a/65b/73b/74b ds30605a-page 150 ? 1998 microchip technology inc. notes:
pic16c63a/65b/73b/74b ? 1998 microchip technology inc. ds30605a-page 151 notes:
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringem ent of patents or other intellectual property rights arising from such use or otherwise. use of microchips products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technolog y inc. in the u.s.a. and other countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. ds30605a-page 152 ? 1998 microchip technology inc. all rights reserved. ?1998, microchip technology incorporated, usa. 8/98 printed on recycled paper. m americas corporate of?e microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 602-786-7200 fax: 602-786-7277 technical support: 602 786-7627 web: http://www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508-480-9990 fax: 508-480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas microchip technology inc. 14651 dallas parkway, suite 816 dallas, tx 75240-8809 tel: 972-991-7177 fax: 972-991-8588 dayton microchip technology inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 detroit microchip technology inc. 42705 grand river, suite 201 novi, mi 48375-1727 tel: 248-374-1888 fax: 248-374-2874 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 714-263-1888 fax: 714-263-1338 new york microchip technology inc. 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 516-273-5305 fax: 516-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 americas (continued) toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905-405-6279 fax: 905-405-6253 asia/pacific hong kong microchip asia paci? rm 3801b, tower two metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2-401-1200 fax: 852-2-401-3431 india microchip technology inc. india liaison of?e no. 6, legacy, convent road bangalore 560 025, india tel: 91-80-229-0061 fax: 91-80-229-0062 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa 222-0033 japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 shanghai microchip technology rm 406 shanghai golden bridge bldg. 2077 yan?n road west, hong qiao district shanghai, prc 200335 tel: 86-21-6275-5700 fax: 86 21-6275-5060 asia/pacific (continued) singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan, r.o.c microchip technology taiwan 10f-1c 207 tung hua north road taipei, taiwan, roc tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44-1189-21-5858 fax: 44-1189-21-5835 france arizona microchip technology sarl zone industrielle de la bonde 2 rue du buisson aux fraises 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 m?chen, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-39-6899939 fax: 39-39-6899883 7/7/98 w orldwide s ales and s ervice microchip received iso 9001 quality system certi?ation for its worldwide headquarters, design, and wafer fabrication facilities in january, 1997. our ?ld-programmable picmicro 8-bit mcus, serial eeproms, related specialty memory products and development systems conform to the stringent quality standards of the international standard organization (iso).

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